Hello. I am glad that someone helps me on this issue. First thank you for the extract you sent me, concerning the CPU2 reset. [quote userid="559325" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1528546/tms320f28379d-watchdog-management/5877277#5877277"]Was CPU2 suspended/halted before the CPU1 WD reset trigger ?[/quote] No, the CPU2 was not halted before the reset happened. [quote userid="559325" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1528546/tms320f28379d-watchdog-management/5877277#5877277"] if you hit run on CPU2 what happens does it reset ?[/quote] Before the reset, the CPU2 is managing a CAN Stack. Everything is working as expected. After the reset, the CPU1 is running although I did not press the run button. If I press the pause button, I can see that it is wating for a IPC acknowledgment, maybe the acknowlegment needed for the IPC_sync function. If I let the CPU1 running et press Run on CPU2, I just can see that the CAN stack does not work. By pressing the pause button, I can see that CPU2 is waiting at the same point than before: I hope that you could help me ! Vincent
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Forum Post: RE: TMS320F28379D: Watchdog Management
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Forum Post: RE: LP-AM261: Manual Reset is needed after loading images to OSPI flash
Is it possible to issue a power on reset from software on AM261? If possible, how we do it? [quote userid="500225" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1529556/lp-am261-manual-reset-is-needed-after-loading-images-to-ospi-flash/5881532#5881532"]without power cycle it is not possible[/quote] Can we use power on reset from software, instead of power cycle?
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Forum Post: RE: HERCULES-F021FLASHAPI: Source Code for the Flash F021 API
Hi Alper, I sent you a friend request, please accept it to get more details from you regarding this on private chat window. -- Thanks & regards, Jagadish.
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Forum Post: LP-AM261: Profinet - Questions Regarding PROFINET Read/Write Record Support
Part Number: LP-AM261 Tool/software: Dear TI Support Team, I am currently working with the LP-AM261 and using the associated SDK ind_comms_sdk_am261x_10_02_00_05 for PROFINET communication. I have a few questions regarding the implementation of Read/Write Record services: Does the PROFINET stack support reading and writing records with large content sizes? What is the maximum supported data size for a single Read or Write Record operation? Does the stack natively support fragmentation of large records, or would this need to be handled at the application level? I would appreciate any clarification on the supported limits and recommendations for handling larger data transfers if fragmentation is not supported natively. Thank you in advance for your support. Best regards J. Zribi
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Forum Post: RE: TMS320F28P550SG: UniFlash 9.1.0: CPU Reset via -r0 not working on TMS320F28P550SG8PZ with XDS200
Yes, it does. No problems.
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Forum Post: RE: TMS320F28P550SG: UniFlash 9.1.0: CPU Reset via -r0 not working on TMS320F28P550SG8PZ with XDS200
Yes, the behavior is exactly the same for me with the ControlCard. The application needs to be restarted.
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Forum Post: LP-AM261: Profinet - Delayed Application Ready
Part Number: LP-AM261 Tool/software: Dear TI Support Team, I am working with the LP-AM261 and its PROFINET stack as provided in the SDK ind_comms_sdk_am261x_10_02_00_05. I have a question regarding the handling of the "Delayed Application Ready" mechanism in the PROFINET implementation. Does the PROFINET stack support delaying the Application Ready signal from the device to the IO-Controller? My use case involves receiving configuration data via Write Record , then processing the Parameter End indication . After that, the application performs internal setup, such as configuring the underlying network interfaces or devices. If an error occurs during this setup phase, is there a way for the application to indicate an error back to the IO-Controller , before signaling Application Ready? (e.g set the erroneous submodules to "ApplicationReady pending" ) Additionally, is it possible for the application to explicitly send the Application Ready signal once the internal setup completes successfully? I would appreciate any clarification on whether this flow is supported by the stack? Best Regards J.Zribi
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Forum Post: TMS320F28069: The chip can work normally when debugging with the XDS100V2 emulator, but it malfunctions when powered solely by the emulator.
Part Number: TMS320F28069 Tool/software: The chip functions properly when debugged using the XDS100V2 emulator. The LCD control function within the RTOS task executes successfully, but the LCD exhibits flickering.When the XDS100V2 emulator is used for power supply without debugging, the LCD light control function in the RTOS task fails to run, and the LCD light does not light up. Here's my CMD code:： . /* //########################################################################### // // FILE: F28067.cmd // // TITLE: Linker Command File For F28067 Device // //########################################################################### // $TI Release: F2806x C/C++ Header Files and Peripheral Examples V135 $ // $Release Date: Sep 8, 2012 $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in \F2806x_headers\cmd // // For BIOS applications add: F2806x_Headers_BIOS.cmd // For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l F2806x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l F2806x_Headers_BIOS.cmd */ /* 2) In your project add the path to \F2806x_headers\cmd to the library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F2806x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28067 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ // The user must define CLA_C in the project linker settings if using the // CLA C compiler // Project Properties -> C2000 Linker -> Advanced Options -> Command File // Preprocessing -> --define #ifdef CLA_C // Define a size for the CLA scratchpad area that will be used // by the CLA compiler for local symbols and temps // Also force references to the special symbols that mark the // scratchpad are. _Cla1Prog_Start = _Cla1funcsRunStart; CLA_SCRATCHPAD_SIZE = 0x100; --undef_sym=__cla_scratchpad_end --undef_sym=__cla_scratchpad_start #endif //CLA_C MEMORY { PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAML3 : origin = 0x009000, length = 0x001000 RAML45 : origin = 0x00A000, length = 0x003000 /*RAML0 : origin = 0x008000, length = 0x000800 on-chip RAM block L0 */ /*RAML1 : origin = 0x008800, length = 0x000400 on-chip RAM block L1 */ /*RAML2 : origin = 0x008C00, length = 0x000400 on-chip RAM block L2 */ /*RAML3 : origin = 0x009000, length = 0x001000 on-chip RAM block L2 */ /*RAML4 : origin = 0x00A000, length = 0x002000 on-chip RAM block L4 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ /*FLASHH : origin = 0x3D8000, length = 0x004000 on-chip FLASH */ /*FLASHG : origin = 0x3DC000, length = 0x004000 on-chip FLASH */ /*FLASHF : origin = 0x3E0000, length = 0x004000 on-chip FLASH */ /* FLASHEND : origin = 0x3E4000, length = 0x000100*/ /* FLASHEND : origin = 0x3E4000, length = 0x000020*/ /*FLASHTYPE : origin = 0x3E4020, length = 0x0000E0*/ FLASHJClr1 : origin = 0x3D8100, length = 0x000100 FLASHJClr2 : origin = 0x3D8200, length = 0x000100 FLASHBCDEFG : origin = 0x3D8348, length = 0x01BCB4 /* on-chip FLASH */ DSPVISION : origin = 0x3D8300, length = 0x4 GOTOMAIN : origin = 0x3D8304, length = 0x4 /* on-chip FLASH */ FLASHEND : origin = 0x3D8308, length = 0x000020 FLASHTYPE : origin = 0x3D8328, length = 0x000020 /*FLASHSTART : origin = 0x3F3FFF, length = 0x01*/ DSP_BOOT : origin = 0x3F5000, length = 0x04 /* on-chip FLASH */ FLASHA : origin = 0x3F5004, length = 0x002F78 /* on-chip FLASH */ FLASH_BOOT : origin = 0x3F3FFC, length = 0x4 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */ IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ RAMM012 : origin = 0x008000, length = 0x001000 /*CLARAM0 : origin = 0x008800, length = 0x000400 on-chip RAM block L0 */ /*CLARAM1 : origin = 0x008C00, length = 0x000400 on-chip RAM block L1 */ /*CLARAM2 : origin = 0x008000, length = 0x000800 on-chip RAM block L2 */ RAML5 : origin = 0x00D000, length = 0x001000 RAML678 : origin = 0x00E000, length = 0x006000 //RAML5678 : origin = 0x00D000, length = 0x007000 /*RAML5 : origin = 0x00C000, length = 0x002000 on-chip RAM block L5 */ /*RAML6 : origin = 0x00E000, length = 0x002000 on-chip RAM block L6 */ /*RAML7 : origin = 0x010000, length = 0x002000 on-chip RAM block L7 */ /*RAML8 : origin = 0x012000, length = 0x002000 on-chip RAM block L8 */ USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */ CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash .TI.ramfunc user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > FLASHBCDEFG, PAGE = 0 .pinit : > FLASHBCDEFG, PAGE = 0 .text : > FLASHBCDEFG, PAGE = 0 codestart : > BEGIN, PAGE = 0 .textJMP1 : > FLASHJClr1 PAGE = 0 .textJMP2 : > FLASHJClr2 PAGE = 0 codeupdate : > FLASHA, PAGE = 0 /* Added by Leon on Nov. 17, 2006 */ dspboot : > DSP_BOOT, PAGE = 0 GotoMain : > GOTOMAIN, PAGE = 0 BOOTFLAG : > FLASH_BOOT, PAGE = 0 // DSPVision : > DSPVISION, PAGE = 0 /*FlashStart : > FLASHSTART PAGE = 0*/ /* Added by Leon on Nov. 17, 2006 */ FlashEnd : > FLASHEND PAGE = 0 FlashType : > FLASHTYPE PAGE = 0 /* added for Special flash flag for Main DSP */ BootRamfuncs : LOAD = FLASHA, RUN = RAMM1, LOAD_START(_Flash28_API_LoadStart), LOAD_END(_Flash28_API_LoadEnd), RUN_START(_Flash28_API_RunStart), PAGE = 0 GROUP { ModuleCodeLib_RAM ramfuncs } LOAD = FLASHBCDEFG, RUN = RAML45, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), RUN_START(_RamfuncsRunStart), PAGE = 0 csmpasswds : > CSM_PWL_P0, PAGE = 0 csm_rsvd : > CSM_RSVD, PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAML5, PAGE = 1 .ebss : > RAML678, PAGE = 1 .esysmem : > RAML678, PAGE = 1 OSStack : > RAML5, PAGE = 1 /* Initalized sections to go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASHBCDEFG, PAGE = 0 .switch : > FLASHBCDEFG, PAGE = 0 /* Allocate IQ math areas: */ IQmath : > FLASHBCDEFG, PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Allocate FPU math areas: */ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD Cla1Prog : LOAD = FLASHBCDEFG, RUN = RAML3, LOAD_START(_Cla1funcsLoadStart), LOAD_END(_Cla1funcsLoadEnd), LOAD_SIZE(_Cla1funcsLoadSize), RUN_START(_Cla1funcsRunStart), PAGE = 0 CLADataRAM : > RAMM012, PAGE=1 Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 #ifdef CLA_C /* CLA C compiler sections */ // // Must be allocated to memory the CLA has write access to // CLAscratch : { *.obj(CLAscratch) . += CLA_SCRATCHPAD_SIZE; *.obj(CLAscratch_end) } > RAMM012, PAGE = 1 .scratchpad : > RAMM012, PAGE = 1 .bss_cla : > RAMM012, PAGE = 1 .const_cla : LOAD = FLASHBCDEFG, RUN = RAMM012, RUN_START(_Cla1ConstRunStart), LOAD_START(_Cla1ConstLoadStart), LOAD_SIZE(_Cla1ConstLoadSize), PAGE = 1 #endif //CLA_C ConstantsInRAM : > RAML678, PAGE = 1 DMARAML8 : > RAML678, PAGE = 1 /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD { IQmath.lib (IQmathTablesRam) } */ /* Uncomment the section below if calling the IQNasin() or IQasin() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD { IQmath.lib (IQmathTablesRam) } */ /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS, PAGE = 0, TYPE = DSECT } /* /* //=========================================================================== // End of file. //=========================================================================== */ The abovementioned issue occurs after adding the following code. #pragma CODE_SECTION(ZeroCrossingInterrupt,"ramfuncs"); interrupt void ZeroCrossingInterrupt(void) { Uint32 dwZeroTemp; dwZeroTemp = ECap1Regs.CAP1; udwOPFrecyIntr = dwZeroTemp - udwLineZeroCrossingOld; if(1 == ECap1Regs.ECFLG.bit.CEVT1) { udwLineZeroCrossingOld = dwZeroTemp; } ECap1Regs.ECCLR.bit.CTROVF = 1; ECap1Regs.ECCLR.bit.INT = 1; ECap1Regs.ECCLR.bit.CEVT1 = 1; ECap1Regs.ECCTL2.bit.REARM = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; }
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Forum Post: RE: MSP430FR2155: Setting up BSL in I2C mode from Application code
Hey, so yesterday I did couple of more tests. Basically, I figured that I2C BSL works when I try to enter it using HW invocation with BSL. I removed I2C init code to test it. Then I enabled jump to BSL from application(I2C still not initialized). Removed TST and RST connection between MSP-FET and device, and tried again. This time it doesn't give an ACK for starting sequence 0x48. I think that indicates that I2C works in general, but something is with activating BSL from app.
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Forum Post: AM2432: Feature support check
Part Number: AM2432 Tool/software: Hi Could you help to check if AM243 support these? Firewall/Router, we want to have some rules to filter out some suspicious network packets to pass through the ethernet port to next device. CDC-ECM, this is important for our project. USB - Ethernet example Regards Zekun
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Forum Post: MSPM0G1106: Device selection request
Part Number: MSPM0G1106 Tool/software: Hi team, Can you suggest proper device which could meet below requirement? Thanks! ARM® Cortex®-M23 32-bit processor core operating at up to 72 MHz frequency, flash 128KB,SRAM 16KB,5 Timer,2 USART,2 I2C, 2/1 SPI/I2S,25 GPIO,16 EXTI,10 ADC, LQFP32,-40 °C to +85 °C
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Forum Post: RE: TMS320F28379D: TMS320F28379D
Hi Masoud, I reviewed the documents, and it states that the pins for the ADC range from 13 to 46. However, I specifically want to confirm the pin for ADCINA2, B2, C2, A5. Based on my tracing, it indicates pin 15 on the docking station for A2. Yet, when I connected to pin 15, the oscilloscope displayed a flat line. Epwm is fine and was showing a signal. Regards
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Forum Post: RE: AM263P4-Q1: HS-SE device failure to access OCRAM banks 4/5
Hi Nikhil, This was with a HSM image generated for the hsm_getversion example. Comparing the hsm_getversion syscfg to the default one under \tifs_am263px_10_00_00_05\hsm_firmware\am263px\hsse\hsm0-0_nortos\example.syscfg, it does seem like many firewall configs are missing. I'm presuming these need to be added in? Will try recompile HSM image with the default firewall config.
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Forum Post: MSP430G2553: Schematic Review
Part Number: MSP430G2553 Tool/software: Hi Team, I would like to seek some help for schematic review, currently there is some issue we face with our part. Is there place where I could send my schematic privately ? Best Regards, JH
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Forum Post: RE: AM2434: Subject: Issue Using External XDS100v2 with AM2434 EVM
Hi Manikandan, Thanks for your query. Please tell us is the EVM properly initialized? Which boot flow are you using? Please share the screenshot of error with complete error logs. Regards, Tushar
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Forum Post: AM2634: CacheP_wbInv should not be called if OS is used, right?
Part Number: AM2634 Tool/software: CacheP_wbInv should not be called if OS is used, right? As you can see the following picture. In the OS folder, there is no CacheP files, but in the no OS folder, there is CacheP files.
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Forum Post: RE: AM2634: CacheP_wbInv should not be called if OS is used, right?
Hi Rick, You can use cacheP apis even with FreeRTOS, This APIs needs to be called if you are using buffers in application and caching is enabled on the memory region.
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Forum Post: RE: AM2634: CacheP_wbInv should not be called if OS is used, right?
As for the if it is included in the project, yes we include all nortos files in freertos as well. Please check the makefiles for that.
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Forum Post: RE: AM2634: CacheP_wbInv should not be called if OS is used, right?
/ti/mcu_plus_sdk_am263x/source/kernel/freertos/makefile.am261x.r5f.ti-arm-clang
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Forum Post: MSPM0L2227: Does clock accuracy improve when the operating temperature range is narrow?
Part Number: MSPM0L2227 Tool/software: Hi All, When using M0 in the range of 5 to 40°C, will the MIN and MAX values of SYSOSC accuracy improve? We expect the accuracy at 5 to 40°C to be better than the accuracy at -40 to 85°C. Best Regards, Ito
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