Hi Toby Grabham, Thanks for your query. Will check on this and get back to by next week. Regards Ashwani
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Forum Post: RE: AM2434: Providing custom MAC address to TI's CPSW driver
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Forum Post: RE: TMS570LS3137: 64 Mailboxes for DCANs
Hi Jagadish, Thanks for the reply! I'm facing one issue, currently the CAN ids on the CAN 3 channel is not more than 13 buffer( including both TX & RX), but as soon we add a new CAN id on CAN 3, the other TX ids of CAN 3 starts flickering, pfa the log for your reference - https://drive.google.com/file/d/1rEcN2UgPx8lywkoHdvQnN_Y4MjtOGNhE/view?usp=drive_link
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Forum Post: RE: F29H850TU: ADC voltage reference (12Bit/16Bit)
Hi Massoud, So you can confirm that this is either incorrect or not quite complete: Or is just the internal voltage reference range limited to 0...2.5V when operating in 16Bit mode? I just want to make sure that I have understood this correctly. Regards, Patrick
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Forum Post: RE: AM263P4-Q1: Unable to Establish Detection for 10BASE-T
Hi Mari, [quote userid="534155" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1528850/am263p4-q1-unable-to-establish-detection-for-10base-t/5880908#5880908"] Would be good to have both the PHY details. (Other end as well as the AM26x connected PHY) [/quote] Q1. Can you confirm the details for the Link partner which is connected to AM263Px? I had a discussion with our PHY team, please find their comments: "For 10M, the link partner must only have 10M auto-negotiation advertisement enabled, If this is not the case, either PHY straps need to be modified, or driver needs to be adjusted" " The SDK PHY drivers looks okay to support 10Base-Te mode. I believe the Link detection might indicate some issues with our configurations (both on the AM263Px as well as the Other side partner)." Q2. Also, would it be possible to get a dump of the PHY-registers for us to review. In some cases, this also helps identify incorrect configs. Regards, Shaunak
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Forum Post: RE: MSPM0G3507: Linker file Configuration of .text region
Hi Pengfei, Thanks to you now customer can run the program normally. Customer would like to add user parameter settings and create flash image for that. For example adding the parameter file between vector table and the program code or create a new image file by combining the parameter file after the first program image (.out, txt file, etc.) generated by the build. Do you have any recommendation what is the best solution for customer? Thank you, Kenley
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Forum Post: MSPM0C1104: SysConfig code-gen fails with “Unexpected identifier” due to typo in resourceUsageReport.csv.xdt
Part Number: MSPM0C1104 Other Parts Discussed in Thread: SYSCONFIG Tool/software: CCS Version: 20.2.0.12__1.8.0 + MSPM0 SDK 2.05: I’m getting an error on build after using the sysconfig tool. Generating Code (msmp0c1104.syscfg)... ...resourceUsageReport.csv.xdt:242 llet resource_IOType = Common.getAttribute(...); ^^^^^^^^^^^^^^^ SyntaxError: Unexpected identifier Line 242 of ti\mspm0_sdk_2_05_00_05\source\ti\driverlib.meta\templates\resourceUsageReport.csv.xdt has a typo. llet instead of let . Patching it fixes the build.
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Forum Post: RE: MSP430F2272-Q1: Guidance Needed for Programming MSP430F2272TRHARQ1 Using LP-XDS110ET and UniFlash
Hi, Thank you for your response. I’ve attached an image of the LP-XDS110ET , which I’m using as a flasher for my custom-designed PCB featuring the MSP430F2272TRHARQ1 . I’ve also included an image of the MSP430F2272TRHARQ1 symbol for your reference.
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Forum Post: TMS320F28377S: Question about Dead Band settings in CCS SysConfig for F28377S
Part Number: TMS320F28377S Other Parts Discussed in Thread: SYSCONFIG Tool/software: Hello, I’m currently working on a project using the F28377S, and I’m configuring ePWM using CCS SysConfig. I have a few questions regarding the Dead Band settings. In SysConfig, there are options like Active High , Active Low , Active High Complementary , and Active Low Complementary . → Could you explain what each mode does and in what situation each one should be used? I noticed that when I select Active Low , both EPWMA and EPWMB signals appear to have the same polarity. → Shouldn't they be inverted in this mode? Or is EPWMB just a hardware-generated signal that's not meant to be used? I'm using only EPWMA in my circuit, but I want to confirm whether these settings affect EPWMA only, or both A and B channels. Also, does the Dead Band polarity setting affect both rising and falling edges, or are there separate controls? Any clarification or documentation link would be greatly appreciated. Thank you in advance! Best regards, Chanwoong Park
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Forum Post: RE: MSPM0L2228: independent watchdog timer (IWDT) disturbs flash process
Hi Sal, unfortunately, this does not solve the problem . If the device is "locked" by IWDT and I start the Wait_for_debug DSSM script, I get the error "Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.0.0.3178)" In the MSPM0 Desing Flow Guide chapter unlock MCU you have mentioned, I did not find something about WDT or WaitForDebg skript. Only EraseFlash and FactoryReset witch also does not work. Enable the function wait for debug in Project properties doesn't help either. I still get various error messages. Also starting MCU in BSL mode with PA18. Any other solutions to work with WDT? Regards, Timo
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Forum Post: RE: AM263P4-Q1: AM263P4-Q1
Hi Rapeti, Do you run into any build issues when you configure UART5 and the IO-expander as shared by Brennan? I see that when I configure the IO expander settings, I get a MACRO redefinition error in ti_board_open_close.h. I believe this is a bug, I would be surprised if you did not have this issue. I am using AM263Px v10.02.00.15 with syscfg 1.23.0 (same as you) Regards, Shaunak
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Forum Post: RE: TMDS243EVM: Customer Board use two DP83867 for EtherNet
Hi Teja, Thanks for your efforts, my issue is fixed. The wrong voltage level of MDIO is caused by the wrong configuration of GBE_PHY1_GPIO0 and GBE_PHY1_GPIO1 by hardware side. Now, my board work well with two DP83867 for EtherNet. BR, Chunyang
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Forum Post: RE: AM2634: Miscellaneous interrupt in Ethernet AM2634
Hi shaunak, 1. We are running into constant Host MISC interrupt after PHY Alive and MAC link UP, to be more specific we are encountering it if we are transmitting based on link i.e., both ports link is UP, suddenly we disconnect 1 cable, still running fine. The interrupt is asserted the moment we plug in the cable. 2. The application we are using is Custom made, derivative of SDK (implemented as bare metal). 3. Our custom hardware has KSZ804FL Phy (Fiber PHY supporting upto 100Mbps, we are using 100-FX mode in it). Yes, we are able to detect events of PHY link up and down. The transmission and reception is also fine if left undisturbed. Regards, Srinivas
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Forum Post: TMS570LC4357-SEP: Clarification on SEU Data Availability
Part Number: TMS570LC4357-SEP Tool/software: In the linked discussion, it was mentioned that SEU test data for the TMS570LC4357-SEP is available in document SPNA249. However, while this document includes information on SEL, it does not appear to contain any data or discussion related to SEU. Would it be possible to obtain a separate report specifically addressing SEU for this device? We don't SEU report for TMS570LS3137 device. But we have SEU test report for TMS570LC4357-SEP BGA package https://www.ti.com/lit/an/spna249/spna249.pdf?ts=1711043400769&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526searchTerm%253DSEU+AND+TMS570%2526nr%253D11
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Forum Post: RE: MSPM0L1228: RAMcode did not respond during flashing 50% of the time
Hi Johnson He, I can tell you that I still see the problem on my side. Maybe you can try to flash a LP-MPSPM0L2228 with a Segger flasher. I'm pretty sure you will get the same error. It would be great if TI can find a solution. Regards, Timo
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Forum Post: RE: MCU-PLUS-SDK-AM243X: MCU-PLUS-SDK-AM243X: Using DP83826 for EtherCat Phy -- Part2
Hi Aaron, My Issue is fixed, after making sure my registers from the PHY as the following, all the matter as solved. BR, Chunyang --------------------------reg list------------------------------ addr: x0000, phy state reg : x3100 addr: x0001, phy state reg : x786D addr: x0002, phy state reg : x2000 addr: x0003, phy state reg : xA131 addr: x0004, phy state reg : x01C1 addr: x0005, phy state reg : xCDE1 addr: x0006, phy state reg : x000F addr: x0007, phy state reg : x2001 addr: x0008, phy state reg : x0000 addr: x0009, phy state reg : x0020 addr: x000A, phy state reg : x0102 addr: x000B, phy state reg : x0000 addr: x000C, phy state reg : x0000 addr: x000D, phy state reg : x0000 addr: x000E, phy state reg : x0000 addr: x000F, phy state reg : x0000 addr: x0010, phy state reg : x0015 addr: x0011, phy state reg : x0108 addr: x0012, phy state reg : x6400 addr: x0013, phy state reg : x2800 addr: x0014, phy state reg : x0000 addr: x0015, phy state reg : x0000 addr: x0016, phy state reg : x0100 addr: x0017, phy state reg : x0049 addr: x0018, phy state reg : x0480 addr: x0019, phy state reg : xCC00 addr: x001A, phy state reg : x0000 addr: x001B, phy state reg : x007D addr: x001C, phy state reg : x05EE addr: x001E, phy state reg : x0102
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Forum Post: RE: MSPM0G3507: ADC value update freeze, using DMA.
Update: I have reduced the overhead from the ADC1_IRQHandler and ecu_al_measurements_load_conversion so that ADC will receive via only single channel ie. 4. But still I am facing the same issue.
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Forum Post: TMS320F28P650DK: CPU1 boot and CPU2 boot
Part Number: TMS320F28P650DK Tool/software: Hi TI Experts, I'm working with the TMS320F28P650D dual-core device and looking to implement SCI boot mode for both the CPU1 and CPU2 cores. My questions are: What are the recommended steps to initiate SCI boot for both the CPU1 and CPU2 cores? Can both cores be independently booted via SCI, or does one core need to boot the other? Is there a reference sequence or example code in the SDK that demonstrates dual-core SCI boot? Are there any specific boot mode pin settings or memory configurations required for dual-core SCI boot? How is the bootloader image supposed to be structured if targeting both cores over SCI? where can i set boot modes for CPU1 and CPU2? Any guidance, documentation links, or example projects would be greatly appreciated. Thanks in advance!
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Forum Post: TM4C129XNCZAD: UART 0
Part Number: TM4C129XNCZAD Tool/software: Hi, I am not able to use UART0. Not receiving data on it. Please suggest if any extra components/ module to be added if any.
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Forum Post: MSPM0G3519: Uniflash load image but not running that image
Part Number: MSPM0G3519 Other Parts Discussed in Thread: UNIFLASH Tool/software: Hi , I am loading CSC and application image from Theia ide. and it run every time. after power on CSC verify the application and application start running. but if I flash CSC and application image from uniflash . uniflash shows load successfully. and if i read back memory i can see both images CSC + app in place. but still app is not running. i am using same bin file which i am using to load from theia ide.
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Forum Post: RE: TMDSCNCD263: CMPSS EPWM_XBAR to connect to specific EPWMs & how to configure an INT_XBAR to trigger a sw interrupt
Hi Justin Apologies, to generate an interrupt based on CMPSS, you need to route through ECAP. You can refer to the following example although it is built with an older version of the SDK(9.2.0.56) and uses a lot of bitfield programming instead of the driverlib. The main goal here is to route the CMPSS trip signal to ECAP, enable ECAP interrupts and then use INT_XBAR to route that ECAP interrupt signal to VIM. e2e.ti.com/.../4263.empty_5F00_am263x_2D00_cc_5F00_r5fss0_2D00_0_5F00_nortos_5F00_ti_2D00_arm_2D00_clang.zip [quote userid="656687" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1529438/tmdscncd263-cmpss-epwm_xbar-to-connect-to-specific-epwms-how-to-configure-an-int_xbar-to-trigger-a-sw-interrupt/5881839#5881839"]Also why is it called XBAR Output, where it seems like this field is the triggering mechanism for the xbar - wouldn't XBAR input make more sense? I'm sure there is a reason that I don't fully understand right now.[/quote] Unfortunately I don't know the exact reason for this, but I take it as what the xbar needs to output. Hope this helps! Regards, Akshit
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