Hi Stefano, Can you please confirm these points: 1. The other module that is connected to the TJ1100 PHY, does it detect a link up on the port that is connected to the TJ1100 PHY? 2. If possible, can you connect an Ethernet cable from a PC to the TJ1100 PHY and observe the value of the MDIO_LINK_REG (0x3001FF0C)? As per the expectation, the bit 2 should be set in that register upon a successful link-up. 3. As a continuation of point 2, can you run some Ping/EIP messaging tests between the PC and the DUT's Port with TJ1100 PHY? Regards Archit Dev
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Forum Post: RE: MCU-PLUS-SDK-AM243X: AM243x LaunchPad - Ethernet/IP adapter generic device mii
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Forum Post: LP-AM243: AM243x LaunchPad (AM243x-LP) and the CC33xx Lx Base Board - issue in Serial monitor output
Part Number: LP-AM243 Tool/software: Hi, I have flashed my code to the Flash memory using the Command prompt while device is in UART boot mode. I got the expected output of flashing. I have attached the image of the output. Then, changed the boot mode to QSPI, then powered on and monitored the output in serial monitor. I'm getting 'some test has failed'. I have attached my setup and output image below.
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Forum Post: RE: TMS320F28388D: Certification of STO Process for SIL 3 – Inquiry on Safety-Certified Tools
Dear Sira, Thank you, for your prompt response. We have decided to implement the CRC functionality manually. I will wait for the response from the CCS expert before marking this issue as resolved. Regards, Wilko
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Forum Post: RE: MCU-PLUS-SDK-AM263X: MCU-PLUS-SDK-AM263X
Hi Susan thanks for your reply. My initial idea was to use one microcontroller unit with 2 separate CPSW. In this way I'm able to replicate the actual configuration (see Ls_architecture.rar) previously attached. The first idea look like this. But if not exists microcontroller with two separare CPSW unit I think the best options could be using 2x MCUs with the CPSW in eswitch mode and 1x TX/RX with MAC2MAC connection as you suggest in the email. The architecture could be the folloeing: But can you suggest me an example to connect two microcontroller AM2634 with a MAC2MAC for internal port and the 2 external PHY port? In the MCU SDK I found example for the connection of one CPSW with 2 externel PHY port but I not able to see the architecture you suggest to us. Regarding the use of PRU-ICSSG we can keep the topic separete. Thanks for all Susan M
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Forum Post: RE: MSP430FR6047: USS ADC Capture
Hi Team, Kindly help me to suggest solution for above post. Thanks
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Forum Post: RE: MSPM0G3519: MSPM0G3519 - BOR check
I would just make sure that the MCU is held in reset until the voltage gets to the proper level, judicious use of the delay might solve the issue.
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Forum Post: RE: MSP432E401Y: Printing Float data in UART display
You might need to increase the stack, sprintf() is a hog.
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Forum Post: RE: TMS320F280039C: Launchpad F280039C can't connect
Hello, What target configuration are you using to connect to the device? Also, please refer to the JTAG Connectivity Debug Guide Table 4-1 for more steps on how to debug. Best, Matt
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Forum Post: RE: MSPM0L1306: GPIO default state
You must have a pullup on the pin.
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Forum Post: RE: TM4C123AE6PM: TM4C123AE6PM
[quote userid="640703" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1468964/tm4c123ae6pm-tm4c123ae6pm"]So In total 32 Hardware filters can be set for receiving.[/quote] Hi, I think you may have a misunderstanding on the definition of a message object vs acceptance filters. Each can module has up to 32 message objects. We don't call the filters. As for receiving, you can configure each message object using acceptance masks to receive up to the length of message ID. For example, you can configure message object 1 to receive any message IDs by configuring the acceptable filter to 0. As another example, you can configure message object 1 only receive message ID that is equal to 0x12 and message object 2 to only receive ID equal to 0x34 and message object 3 to receive ID equal to 0x56. 1 7.3.6 Accepting Received Message Objects When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into the CAN controller, the message handling capability of the controller starts scanning the message RAM for a matching valid message object. To scan the message RAM for a matching message object, the controller uses the acceptance filtering programmed through the mask bits in the CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid message object, starting with object 1, is compared with the incoming message to locate a matching message object in the message RAM. If a match occurs, the scanning is stopped and the message handler proceeds depending on whether it is a data frame or remote frame that was received.
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Forum Post: RE: TMS320F28P550SJ: The uniflash tool can not access the device
[quote userid="8648" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1463295/tms320f28p550sj-the-uniflash-tool-can-not-access-the-device/5637169#5637169"] However they changed the MCU the isssued was then solved.[/quote] It may be a defective part. I will defer to the C2000 team for any further insight here.
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Forum Post: RE: LP-MSPM0L2228: I2C stop condition enable/disable
You're getting a NACK, so the I2C unit automatically terminates the transaction. According to FXLS8964AF datasheet (rev 3.4) Sec 12.1, its I2C address is 0x18 (or 0x19 if SA0=1). Unsolicited: In most cases, such a piecewise transaction can be done (with fewer headaches) using the RD_ON_TXEMPTY feature. [Ref TRM (SLAU847D) Sec 21.2.4.1.3] Briefly: 1) Enable the feature: DL_I2C_resetControllerTransfer(I2C_INST); // Set MCTR=0 to avoid enableControllerReadOnTXEmpty hazard DL_I2C_enableControllerReadOnTXEmpty(I2C_INST); // Write then read 2) Write the register address to the Tx FIFO 3) Perform the Rx transaction with DL_I2C_startControllerTransfer() [don't count the Tx FIFO contents in the length] 4) Disable the feature [I'm not sure this is needed, but it seems proper] [Same as above but using DL_I2C_disableControllerReadOnTXEmpty()] DL_I2C_resetControllerTransfer(I2C_INST); // Set MCTR=0 to avoid disableControllerReadOnTXEmpty hazard DL_I2C_disableControllerReadOnTXEmpty(I2C_INST); // Turn off Repeated Start feature [Edit: Insert code for (4) since E2E didn't allow that before(?)]
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Forum Post: RE: MCU-PLUS-SDK-AM243X: AM243x LaunchPad - Ethernet/IP adapter generic device mii
Hi, Other modules does not detect link up Regards. Stefano
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Forum Post: RE: TMS320F28374D: Control for both Duty Cycle and Phase shift
Hi Eric, Thanks for the follow up! I will post a few notes from our mail thread here in case this thread is referred to in the future Regarding my first response above, the diagram posted was not specific to HR as CMPAHR is only for channel A and CMPBHR is for channel B. The desired use case was actually that channel B is phase shifted relative to the channel A (rather than EPWMx to EPWMy level), so phase shift and duty cycle adjustment will be done on one channel. The phase shift and duty cycle changes are also variable, not static and will be updated frequently ~every cycle. My input is that the EPWM phase shift hardware (TBPHS and TBPHSHR) is only applied between two separate EPWM modules , not between EPWM channels A and B. I don’t see an easy way to implement both HR phase shift and duty control at the same time for two separate PWM modules given the HR control mode registers. However, since the customer is using a single EPWM module, they could implement “phase shift” between channels A and B using half-cycle clocked Dead Band and then apply duty control using CMPAHR/BHR. Also, we do not have a specific example showcasing this, but there is an example applying regular dead band while also using HR duty control in the latest C2000Ware (C2000WARE_ROOT\driverlib\f2837xd\examples\cpu1\hrpwm\hrpwm_ex9_dutyhr_updown_deadband_sfo. Feel free to mark this as resolved to help close the thread! Best Regards, Allison
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Forum Post: RE: TMS320F28379D: Synchronizing the EPWM1 with External Sync In
Hi Allison! The issue has been resolved. It was actually a silly mistake- didnt called the function. The ePWM1A is now synchronized with the external trigger, however, the ADC stopped getting triggered by the ePWM1A now.
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Forum Post: SAFETI-HALCOGEN-CSP: Safety Caseis not included in the CSP package.
Part Number: SAFETI-HALCOGEN-CSP Other Parts Discussed in Thread: HALCOGEN Tool/software: Hello TI team, We are under the process of certifying our product that makes use of HalcoGen in our product. For provinf that we fulfil the expectation of a successful compliance to ISO26262, we refer to the Safety Manual document from TI. HALCoGen Software Safety Manual for Hercules Family of Microcontrollers Literature number: SPNU593A We are using Halcogen Package version: 04.07.01 In this document, it says that given a valid NDA in place, we should be able to receive a 'Safety Case' document from TI in the compliance support package. We received all the other documents as shown in section C.4., Table 10, but not the safety case. Could you please share that with us for the said version?
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Forum Post: TMS570LS0432: Safety Case is missing in the CSP package.
Part Number: TMS570LS0432 Tool/software: Hello TI team, We are under the process of certifying our product that makes use of SafetTI library in our product. For proving that we fulfil the expectation of a successful compliance to ISO26262, we refer to the Safety Manual document from TI. Name of the document: SafeTI Diagnostic Library Software Safety Manual for Hercules Processors Literature number: SPNU592A We are using SafeTI library version : 2.4.0 In this document, it says that given a valid NDA in place, we should be able to receive a 'Safety Case report' document from TI in the compliance support package. We received all the other documents as shown in section C.4., Table 10, but not the safety case report. Could you please share that with us for the said version?
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Forum Post: TMS320F28388D: Problem using "IPC message copy to RAM boot" to start CM
Part Number: TMS320F28388D Tool/software: Hi im trying to boot a quite simple program to the using the "IPC message copy to RAM boot" method ,i do the following actions: 1.I use the armhex tool to create and array out of the program. 2.I fix the array as it created with uin8_t type cmds and it should be uint16_t (before i fixed it Ive got a "Hard fault occurred" status). 3.I copy the fixed array to CPU1TOCMMSGRAM1 at address 0x00039400. 4.I configure the CPU1TOCMIPCBOOTMODE to the following value:0x5A02640C , which states 100Mhz freq and 200 words copy. 5.Reset the CM (Tried both with and without). 6.Set CPU1TOCMIPCFLG0 flag0 to start the copying. What i see is that CPU1TOCMMSGRAM1 receives the array ,but the copying doesnt happen, since address 0x20000800 in the CM which is the destination of the copy is filled with zero's only. Am i missing some part of the process i followed the manual and tried to check other posts but to no avail. Any help will be much appreciated.
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Forum Post: RE: EK-TM4C1294XL: questions regarding ethernet use in freeRTOS
Hi Ping, The bare-metal enet_lwip has been converted for FreeRTOS. Can you take a look at this app note Developing Advanced Applications With FreeRTOS on TM4C MCUs ?
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Forum Post: RE: TMDSCNCD263P: OSPI bootloader not working/executing from flash
Hi Rens, Apologies you had a face this issue, we identifued this bug lates last week and we are working on making the updated release to fix it.
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