The issue is happening due to boards version mismatch, As the new revision of Control card has similar flash reset mechanism as am263px-lp. So for the meanwhile you can use the following workaround: 1. In syscfg( examples\drivers\boot\sbl_ospi\am263px-cc) add the following GPIO pin: gpio1.pinDir = "OUTPUT"; gpio1.$name = "GPIO_OSPI_RST"; gpio1.defaultValue = "1"; gpio1.GPIO_n.$assign = "EPWM11_B"; 2. Then in SBL OSPI example replace the file examples\drivers\boot\sbl_ospi\am263px-cc\r5fss0-0_nortos\board.c with the file: C:\ti\mcu_plus_sdk_am263px_10_00_00_35\examples\drivers\boot\sbl_ospi\am263px-lp\r5fss0-0_nortos\board.c 3. Rebuild the example For flash example same thing needs to be done, Let me know if this helps.
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Forum Post: RE: TMDSCNCD263P: OSPI bootloader not working/executing from flash
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Forum Post: RE: TM4C1230C3PM: Flash a .hex file to TM4C1230C3PM
HI, I also tried with the 10 pin adapter but the result is the same. Do you have any other TI boards with a 10pin JTAG header on it? It does not have to be EK-TM4C123GXL. I just wanted to know if your problem is related to the debug probe you have. I'm using uniflash 9.0.0.5086 and XDS200 from blackhawk. That should be fine. Is there any advice on the drivers to follow? Are the drivers integrated with uniflash? Follow this webpage if you need to update the driver and see if that resolves the problem. https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds200.html I select "Texas Instruments XDS2xx USB Debug probe" from the connection list. Is this correct? Correct.
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Forum Post: RE: MSPM0L2228: Can no longer debug anything, call stack indicating 0xFFFFFFF8
Hi Chris, We'll support this E2E internally. Best Regards, Diego Abad
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Forum Post: RE: MSP430F5529: CCS Set Resource Explorer Import path default
Hi David, I see. In that case, I would either reinstall CCS and see if this solves this issue or manually move the project you get from Resource Explorer from Home to your desired workspace. Sadly, there is no option to change where Resource Explorer creates a project. By default, it should go towards the workspace you are using. Best Regards, Diego Abad
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Forum Post: RE: MSP430F5529: CCS Set Resource Explorer Import path default
I've actually gone a little farther than that. I have installed CCS on the ${DATA} drive. There is no ${HOME}/ti directory normally, except if I import an example. Then, it creates one. Guess I'll just live with it.
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Forum Post: TMS320F28P650DK: EtherCat and SSC by BeckOff
Part Number: TMS320F28P650DK Other Parts Discussed in Thread: DP83822IF Tool/software: Hello support team, before approaching my question, let me make an introduction about the setup. I use SSC tool by Beckhoff Automation Gmbh, and an Excel file to generate a XML file to load on DP83822IF by TI. The ESC device supports the F28P65 for EtherCat communication. Since some days ago, I have faced with the issue returned during the Xml file generation. Failed to patch file "ecatslv.c" | Unknown patch line ' ', expect '+', '-', ' ' or '@' So my question is: why does the tool return this error ? What does it mean ? Below the entire message from LLC tool. Failed to patch file "ecatslv.c" | Unknown patch line ' ', expect '+', '-', ' ' or '@' "aoeappl.c" : skipped (AOE_SUPPORTED) "aoeappl.h" : skipped (AOE_SUPPORTED) "bootmode.c" : skipped (BOOTSTRAPMODE_SUPPORTED) "bootmode.h" : skipped (BOOTSTRAPMODE_SUPPORTED) "bootloaderappl.c" : skipped (BOOTLOADER_SAMPLE) "bootloaderappl.h" : skipped (BOOTLOADER_SAMPLE) "cia402appl.c" : skipped (CiA402_SAMPLE_APPLICATION) "cia402appl.h" : skipped (CiA402_SAMPLE_APPLICATION) "diag.c" : skipped (DIAGNOSIS_SUPPORTED) "diag.h" : skipped (DIAGNOSIS_SUPPORTED) "ecataoe.c" : skipped (AOE_SUPPORTED) "ecataoe.h" : skipped (AOE_SUPPORTED) "ecateoe.c" : skipped (EOE_SUPPORTED) "ecateoe.h" : skipped (EOE_SUPPORTED) "ecatfoe.c" : skipped (FOE_SUPPORTED) "ecatfoe.h" : skipped (FOE_SUPPORTED) "ecatsoe.c" : skipped (SOE_SUPPORTED) "ecatsoe.h" : skipped (SOE_SUPPORTED) "emcy.c" : skipped (EMERGENCY_SUPPORTED) "emcy.h" : skipped (EMERGENCY_SUPPORTED) "eoeappl.c" : skipped (EOE_SUPPORTED) "eoeappl.h" : skipped (EOE_SUPPORTED) "fc1100hw.c" : skipped (FC1100_HW) "fc1100hw.h" : skipped (FC1100_HW) "foeappl.c" : skipped (FOE_SUPPORTED) "foeappl.h" : skipped (FOE_SUPPORTED) "mcihw.c" : skipped (MCI_HW) "mcihw.h" : skipped (MCI_HW) "testappl.c" : skipped (TEST_APPLICATION) "testappl.h" : skipped (TEST_APPLICATION) "sampleappl.c" : skipped (SAMPLE_APPLICATION) "sampleappl.h" : skipped (SAMPLE_APPLICATION) "fc11xxAccess.dll" : skipped (FC1100_HW) "fc11xxAccess.h" : skipped (FC1100_HW) "fc11xxAccess.lib" : skipped (FC1100_HW) "EtherCATSampleLibrary.h" : skipped (SAMPLE_APPLICATION_INTERFACE) "SampleApplicationInterface.c" : skipped (SAMPLE_APPLICATION_INTERFACE) "SampleApplicationInterface.h" : skipped (SAMPLE_APPLICATION_INTERFACE) "applInterface.h" : new file written "mailbox.c" : new file written "coeappl.c" : new file written "coeappl.h" : new file written "ecatappl.c" : new file written "ecatappl.h" : new file written "ecatcoe.c" : new file written "ecatcoe.h" : new file written "ecatslv.c" : new file written "ecatslv.h" : new file written "el9800appl.c" : new file written "el9800appl.h" : new file written "el9800hw.c" : new file written "el9800hw.h" : new file written "esc.h" : new file written "mailbox.h" : new file written "objdef.c" : new file written "objdef.h" : new file written "sdoserv.c" : new file written "sdoserv.h" : new file written Generate files finished Create device description finished "C:\ ............ \.....CatSlaveDCDC.xml" Create Slave files finished Thank you very much for your support, Ettore
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Forum Post: TMS320F28379D: ADC not getting triggered by ePWM while ePWM is being external synch triggered
Part Number: TMS320F28379D Tool/software: Dear Experts, I was trying to synchronize ePWM1 with an external sync(GPIO18) via Xbar and it got synchronized. However, the ADC which had been triggered with ePWM TBCTR is no more being triggered after Xbar is incorporated. Please do the needful. Here is the code: #include "F28x_Project.h" extern void InitSysCtrl(void); extern void InitPieCtrl(void); extern void InitPieVectTable(void); interrupt void TimerOvf(void); interrupt void ADCs_EOC(void); void Initialize_GPIO(void); void Custom_Init(void); void timer0_init(void); void PWM1_Init(void); void Init_ADCs(void); void X_bar(void); int b=0; float a=0; void main(void) { InitSysCtrl(); Custom_Init(); PWM1_Init(); Init_ADCs(); DINT; Initialize_GPIO(); InitPieCtrl(); IER = 0x0000; IFR = 0x0000; InitPieCtrl(); InitPieVectTable(); EALLOW; PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //ADC-A1 PieCtrlRegs.PIEIER1.bit.INTx7 = 1; PieCtrlRegs.PIEIER3.bit.INTx1 = 1; PieVectTable.TIMER0_INT = &TimerOvf; PieVectTable.ADCA1_INT = &ADCs_EOC; PieCtrlRegs.PIECTRL.bit.ENPIE= 1; EDIS; IER |= 3; EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM timer0_init(); CpuTimer0Regs.TCR.bit.TSS=0; while(1) { } } void Initialize_GPIO(void) { EALLOW; //GPIO 18 - Xbar input GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; GpioCtrlRegs.GPADIR.bit.GPIO18 = 0; GpioCtrlRegs.GPACSEL3.bit.GPIO18 = 0; GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; InputXbarRegs.INPUT5SELECT = 18; GpioCtrlRegs.GPADIR.bit.GPIO18 = 0; // LED out GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; GpioCtrlRegs.GPADIR.bit.GPIO31 = 1; GpioCtrlRegs.GPCDIR.bit.GPIO73= 1; //PWMs GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //ePWM1A GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; //ePWM1A GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; //ePWM2A EPwm1Regs.CMPA.bit.CMPA = 1500; EPwm2Regs.CMPA.bit.CMPA = 500; EDIS; } void Custom_Init(void) { EALLOW; ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1; ClkCfgRegs.AUXPLLMULT.bit.IMULT=20; ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0; ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2; ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0; CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; ///source initsysctrl CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; CpuSysRegs.PCLKCR13.bit.ADC_A = 1; CpuSysRegs.PCLKCR0.bit.CLA1 = 1; DevCfgRegs.CPUSEL0.bit.EPWM1 = 0; EDIS; } void timer0_init(void) { EALLOW; CpuTimer0Regs.PRD.bit.MSW = 0x0004; CpuTimer0Regs.PRD.bit.LSW = 0x0080; CpuTimer0Regs.TPR.bit.TDDR = 0x0013; CpuTimer0Regs.TCR.bit.TIE= 1; CpuTimer0Regs.TCR.bit.TSS=1; CpuTimer0Regs.TCR.bit.FREE=0; CpuTimer0Regs.TCR.bit.TRB=0; EDIS; } void TimerOvf(void) { b= b+1; if(b>3) { EPwm1Regs.TBSTS.bit.SYNCI=1; b=1; } if(EPwm1Regs.TBSTS.bit.SYNCI==1) { GpioDataRegs.GPBSET.bit.GPIO34=1; GpioDataRegs.GPASET.bit.GPIO31=1; } CpuTimer0Regs.TCR.bit.TIF = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; } void ADCs_EOC(void) { a = AdcaResultRegs.ADCRESULT0; //Va EPwm1Regs.CMPA.bit.CMPA = 10000*a/4095; EPwm2Regs.CMPA.bit.CMPA = 10000*a/4095; EPwm4Regs.CMPA.bit.CMPA = 10000*a/4095; AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; } void PWM1_Init(void) { EALLOW; EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up EPwm1Regs.TBPRD = 10000; // Set timer period EPwm1Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTR = 0x0000; // Clear counter EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 0; EPwm1Regs.TBCTL.bit.SYNCOSEL = 0; // Setup shadow register load on ZERO EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; EPwm1Regs.CMPCTL.bit.LOADAMODE = 0; EPwm1Regs.CMPCTL.bit.LOADBMODE = 0; // Set Compare values // Set compare A value // Set actions EPwm1Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero EPwm1Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count //SOCA to ADC EPwm1Regs.ETSEL.bit.SOCAEN=1; EPwm1Regs.ETSEL.bit.SOCASEL=1; EPwm1Regs.ETPS.bit.SOCAPRD = 1; EPwm1Regs.ETCLR.bit.SOCA = 1; EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Count up EPwm2Regs.TBPRD = 8000; // Set timer period EPwm2Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0 EPwm2Regs.TBCTR = 0x0000; // Clear counter EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = 0; EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // Setup shadow register load on ZERO EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0; EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0; EPwm2Regs.CMPCTL.bit.LOADAMODE = 0; EPwm2Regs.CMPCTL.bit.LOADBMODE = 0; // Set Compare values+ // Set compare A value // Set actions EPwm2Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero EPwm2Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count EDIS; } void Init_ADCs(void) { EALLOW; AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1; AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1; AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1; DELAY_US(1000); AdcaRegs.ADCCTL2.bit.PRESCALE = 6; AdcbRegs.ADCCTL2.bit.PRESCALE = 6; AdccRegs.ADCCTL2.bit.PRESCALE = 6; AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0 AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert pin A1 AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert pin A2 AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert pin A3 AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC4 will convert pin A4 AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //SOC5 will convert pin A5 AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin B2 AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin B3 AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin B4 AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin B5 AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin C2 AdccRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin C3 AdccRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin C4 AdccRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin C5 AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1; AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 11; AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 05; AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1; AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 11; AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =05; AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1; AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 11; AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =05; AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared EDIS; } Thanks in advance. Regards, Rajesh.
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Forum Post: RE: TMS320F28379D: Not able to upload .out file in both CPU.
Hi Kashyap, GPIO 72/84 is configured to be pulled high/low externally by the boot switches, assuming you haven't programmed the OTP. Are you attempting to load to a LaunchPad, ControlCard, etc? Is CPU1 running code successfully? Best, Matt
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Forum Post: RE: TMS320F28335: SCI Bootloader without Boot mode Pins
I will be closing this thread as its been several weeks without a reply and assume to be resolved.
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Forum Post: RE: MSP432E401Y: TLS Server Name Indication
I've made some progress. I found that the SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME attribute actually does set the SNI. I used the SlNetSock_secAttribSet function to set the value before making the connection. I stepped through this and watched it load the value properly. Then I made the call to connect the socket and in the SlNetIfNDK_sockStartSec, where the domain name should be loaded, the attribute is no longer set. I hacked in the pointer to my domain name string for a test and found that the SNI was properly generated during the connect process. Can you explain why the attribute that is set with SlNetSock_secAttribSet is not present when SlNetIfNDK_sockStartSec gets called?
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Forum Post: RE: F29H85X-SOM-EVM: ADC is not working properly
Hi Martin, Please find my Replies below for the Queries: [quote userid="631373" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1468707/f29h85x-som-evm-adc-is-not-working-properly"]Incorrect voltage on VREFHIAB and VREFHICDE pins when external VREF mode is selected[/quote] It's a Known issue with MCU114 E1 version, it is corrected for Revision A board. [quote userid="631373" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1468707/f29h85x-som-evm-adc-is-not-working-properly"]A6 is in the pin 15 and A7 is in the 17. So that explain why A6 is changing when I inject a signal on the pin 15 but why it also change A7.[/quote] If you check the voltage using a Multimeter/OScope on A7 do you see a voltage on this pin ? Can you ground pin A7 and see if you still get correct ADC codes for A7 & A6 ? BR, Nilesh
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Forum Post: RE: F29H85X-SOM-EVM: ADC is not working properly
Please refere this for vrefhi issue --> Link
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Forum Post: TMS570LC4357: TMS570LC43 Safety Library
Part Number: TMS570LC4357 Other Parts Discussed in Thread: HALCOGEN , TMDX570LC43HDK Tool/software: I am attempting to use the SafeTI start up test code generated by Halcogen in conjunction with the Halcogen derived UART example. I am using the TI compiler with CCS 12.8.1.00005 and the TMDX570LC43HDK dev board. If I enable any of the start up safety tests, the debug symbols on the task bar are all greyed out and the program does not run. It is not possible to set break points or view registers. This is the case with both debug and release builds. If however I disable some of the start up tests, and reset the board (either a system reset or power on reset) the red error LED lights fleetingly and the release program does indeed run. This is the working combination of tests which I have arrived at by trial and error: #define STC_ENABLE 1 #define PBIST_ROM_ENABLE 1 #define PBIST_L2RAM_ENABLE 1 #define PBIST_PERIPHRAM_ENABLE 0 #define PBIST_VIM_ENABLE 0 #define L2RAMECCCHECK_ENABLE 1 #define FLASHECCCHECK_ENABLE 1 #define PERIPHRAMECCCHECK_ENABLE 0 #define EFUSETEST_ENABLE 0 #define CCMR5TEST_ENABLE 1 Is this the expected behaviour? If not, what should I be doing beyond following the instructions in the examples to permit debugging and enable all safety tests?
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Forum Post: RE: TMS320F28P550SJ: Questions on F28P55 128PIN VREFHI/VREFLO & MUX position(default fault function) & ALT
Hi Zane, You are right about the DAC, we don't have an option to use any reference apart form VREFHI pins. So we can't use reference pins as ADC inputs in that case. BR, Nilesh
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Forum Post: RE: LAUNCHXL-F28379D: DCSM Security Tool
Yeah, that clicked once I saw that. I didn't think about the reset being the default operation when I was working on this, but it definitely makes sense now. Thank you for you help!
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Forum Post: RE: LP-AM263P: Not able to select the right Part Number for kit MCU in CCS
SDK Version : mcu_plus_sdk_am263px_10_01_00_31 CCS Version : 12.8.1.00005 Boot Version :
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Forum Post: RE: AM2634-Q1: Multicore Image Execution and Best Practices for Core Utilization
Hello Perumalsamy, 1) [quote userid="640416" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1468647/am2634-q1-multicore-image-execution-and-best-practices-for-core-utilization/5637177#5637177"]In this case the tasks will run only on R5FSS0-0 or it will be shared across all cores. [/quote] I don't understand this statement. Could you perhaps provide a high-level diagram describing the system/application expectation here? Cores, Tasks, Peripherals, etc... 2) This is possible, but the binaries must run on one (or both?) of the 2 cores in each cluster and be designated as such from the system project configuration. We may be able to elaborate after better understanding the requirements from Q1. Best Regards, Zackary Fleenor
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Forum Post: RE: TMS320F28P650DK: Sysconfig MCAN board.c
Hello Wee Khee Ho, Thank you for pointing this out. I will replicate this issue on my end and check with the software dev team if this behavior is expected (seems unlikely). I will follow up within the week or once more information is available. Best Regards, Zackary Fleenor
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Forum Post: TM4C129ENCPDT: NDK_Send blocking - using a mailbox within the tcpEcho example
Part Number: TM4C129ENCPDT Tool/software: Hello, I am modifying the TI-RTOS tcpEcho function. In short, I have two tasks: a tcp task, and a UART task. This is the same tcp task that is originally with the tcpEcho example. In summary, I want to echo whatever the tcp socket receives out of both the tcp socket, and the UART. Please note that these are separate tasks, and UART is at a lower priority. The problem I have encountering is that the "send" function, which calls NDK_send, does not appear to be blocking. Because of this, the tcp task is put to sleep before the send function has finished. This is creating timing issues, or appears to be. Questions: 1) can I make the send function blocking? 2) Is there a status or callback that indicates when the send function is done? Below is my current code. I've commented out the mailbox related items. Thank you! //============================================================================= /** @return - Void Task to handle TCP connection. Can be multiple Tasks running this function. */ Void tcpWorker ( UArg arg0, /// 0) { /* TCP Echo Functionality */ bytesSent = send(clientfd, tcpTaskSys.buffer.x, bytesRcvd, 0); if ((bytesSent < 0) || (bytesSent != bytesRcvd)) { System_printf("Error: send failed.\n"); /* SysMin will only print to the console when you call flush or exit */ System_flush(); break; //loopError = true; } //else //{ /* EGSE Code */ //mailboxPostSuccess = Mailbox_post(*(tcpTaskSys.rs422Handle), tcpTaskSys.buffer.x, BIOS_NO_WAIT);//sizeof(buffer)); //TODO double check the sizeof(buffer) statement. //if (true == mailboxPostSuccess) //{ //System_printf("Mailbox post to RS422 successful.\n"); /* SysMin will only print to the console when you call flush or exit */ //System_flush(); //Task_sleep(GetSleepTickCount()); //} //else //{ //TODO if the mailbox is full, add push to FIFO here //System_printf("Mailbox error!\n"); /* SysMin will only print to the console when you call flush or exit */ //System_flush(); //} // } } System_printf("tcpWorker stop clientfd = 0x%x\n", clientfd); close(clientfd); }
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Forum Post: RE: TMS570LS3137: SAFETI-HALCOGEN-CSP Information Request
Hi Jagadish, Thanks for your help on this! That's great news! As mentioned in the second forum post you've attached, we are met with an export approval page when attempting to download either the SAFETI-HALCOGEN-CSP or SAFETI-HERCULES-DIAG-LIB-CSP which details the previously mentioned licensing fees of $12,000 / $25,000. How should we proceed? Thanks and best regards, Tyler
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