Part Number: TMS320F28379D Other Parts Discussed in Thread: TEST Hello Everyone, I am trying to receive array from docklight software But, the last byte of array is not receiving initially. baud rate is 9600, parity none,stop bit 1. For ex. if I send "Hello" from docklight software. The microcontroller received "Hell" only. again if I send "Hello" controller receive "oHell". it means the last byte of array will receive with second array. I have attached my code for your ref. #include "F28x_Project.h" // Globals //So, Tpwm = (2001) / (12.5M) = 0.00016 //Fpwm = 1/Tpwm = 1/0.00016 = 6.246 kHz //so to find count from freq // count (tbprd)= 12.5MHz/ freq .... where tbprd=max+min char ReceivedChar[1000]; char *msg; int j; // Function Prototypes void Scic_echoback_init(void); void Scic_xmit(int a); void Scic_msg(char *msg); interrupt void scicRxFifoIsr(void); void main(void) { // Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks // This example function is found in the F2837xD_SysCtrl.c file. InitSysCtrl(); // Step 2. Initialize GPIO: // This example function is found in the F2837xD_Gpio.c file and // illustrates how to set the GPIO to it's default state. InitGpio(); // For this example, only init the pins for the SCI-A port. // GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits // GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS // These functions are found in the F2837xD_Gpio.c file. GPIO_SetupPinMux(139, GPIO_MUX_CPU1, 6); GPIO_SetupPinOptions(139, GPIO_INPUT, GPIO_PUSHPULL); GPIO_SetupPinMux(56, GPIO_MUX_CPU1, 6); GPIO_SetupPinOptions(56, GPIO_OUTPUT, GPIO_ASYNC); // Enable PWM1, PWM6 CpuSysRegs.PCLKCR2.bit.EPWM1=1; CpuSysRegs.PCLKCR2.bit.EPWM6=1; // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3 // These functions are in the F2837xD_EPwm.c file InitEPwm1Gpio(); InitEPwm6Gpio(); // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts DINT; // Initialize the PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the F2837xD_PieCtrl.c file. InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this example. This is useful for debug purposes. // The shell ISR routines are found in F2837xD_DefaultIsr.c. // This function is found in F2837xD_PieVect.c. InitPieVectTable(); // Interrupts that are used in this example are re-mapped to // ISR functions found within this file. EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.SCIC_RX_INT = &scicRxFifoIsr; EDIS; // This is needed to disable write to EALLOW protected registers // To ensure precise timing, use write-only instructions to write to the entire // register. Therefore, if any of the configuration bits are changed in // ConfigCpuTimer and InitCpuTimers (in F2837xD_cputimervars.h), the below // settings must also be updated. CpuTimer0Regs.TCR.all = 0x4001; // Enable global Interrupts and higher priority real-time debug events: IER = M_INT8 ; // For ADCA0,EPWM1 and for SCIC_RX // Enable interrupts for SCI/UART required for this example PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // PIE Group 8, INT1 SCI RX.. see page no. 96 Scic_echoback_init(); // Initialize SCI for echoback EINT; // Enable Global interrupt INTM ERTM; // Enable Global real-time interrupt DBGM while(1) { } } // Scic_echoback_init - Test 1, SCIC DLB, 8-bit word, Baud rate 0x000F, default,1 STOP bit, no parity void Scic_echoback_init() { // Note: Clocks were turned on to the Scic peripheral // in the InitSysCtrl() function ScicRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback // No parity,8 char bits, // async mode, idle-line protocol ScicRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK, // Disable RX ERR, SLEEP, TXWAKE ScicRegs.SCICTL2.all = 0x0003; // ScicRegs.SCICTL2.bit.TXINTENA = 1; ScicRegs.SCICTL2.bit.RXBKINTENA = 1; //Scic at 9600 baud //pllsysclk=100MHZ by sysctrl register //sysclk is 100MHz //lspclk=100/4=25Mhz. //baud=LSPCLK/(9600 * 8) - 1 //LSPCLK uses a /4 divider by default ScicRegs.SCIHBAUD.all = 0x0001; ScicRegs.SCILBAUD.all = 0x0045; ScicRegs.SCIFFTX.all = 0xE040; //0xE040 ScicRegs.SCIFFRX.all = 0x0022; //0x2044; ScicRegs.SCIFFCT.all = 0x0; ScicRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset ScicRegs.SCIFFRX.bit.RXFIFORESET = 1; } // Scic_xmit - Transmit a character from the SCI void Scic_xmit(int a) { while (ScicRegs.SCIFFTX.bit.TXFFST != 0) {} ScicRegs.SCITXBUF.all =a; } // Scic_msg - Transmit message via Scic void Scic_msg(char * msg) { int i; i = 0; while(msg[i] != '\0') { Scic_xmit(msg[i]); i++; } } // scicRxFifoIsr - Scic Receive FIFO ISR interrupt void scicRxFifoIsr(void) { while(ScicRegs.SCIFFRX.bit.RXFFST == 0) { } // wait for empty state ReceivedChar[j] = ScicRegs.SCIRXBUF.all; j++; ScicRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag ScicRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag PieCtrlRegs.PIEACK.all|=M_INT8; // Issue PIE ack }
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Forum Post: TMS320F28379D: SCI Commuication: Last byte of array not receiving
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Forum Post: RE: MSP-EXP430F5529LP: How to program the Timer0_B7 CC0 interrupt
How did I miss P3.5/6! Yes I just looked at the run of CPU pins from 55 to 59 giving TB0.0 to TB0.4 - and never went on to find TB0.5 and 6! I may well use that, I've 100Hz sine waves coming out on all of these pins, but with subtle phase relations between some, and it would be good to be test! This said, more worried about timing right now; the target for operation is the pwm period, and interrupt to 100kHz, now the development board is an order of magnitude slower - so only aiming for a 10kHz interrupt. But even doing that needs *very* careful timing - and I think I'm just missing right now ... I'll have to look into port mapping, how its implemented (e.g. is it in hardware), and any effects on timing. Thanks for the help and suggestions though.
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Forum Post: RE: TM4C129XNCZAD: DFU enumeration failure with TM4C129
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Forum Post: RE: TMS320F28379D: Usage of extern C neglects the content of header file
Hi John, thank you for your answers. I understand now. So, I tried to treat only one variable of the x.h file as 32 bit wide and then the inclusion of x.h, but seems the compiler is skipping all the header file content, is it because of the compiler bug? #ifdef __cplusplus extern 'C' unsigned long ANYVARIBALE; // this is used and declared in x.h #include "x.h" #endif Since GCC compiler is defining 'ANYVARIABLE ' as 64-bit, while C2000 as 16 bit, what could be another way to tell the compiler that for only that variable it has to define as 64 bit and the rest of others as it is. Because the main problem is I cannot modify the x.h file, otherwise In the header itself I would have defined it for that particular variable. Thanking you VP
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Forum Post: RE: TMS570LC4357: ADC10 Parity Bits memory mapping not clear
Hi QJ, Flipping the LSB works for me only with an 8Bit access to Parity Ram, if I try it with a 32bit access nothing happens. Does the Parity Ram only support 8bit access? Also, the Reference Manual suggest, there are 2 parity bits for a 32bit word (1bit for 16bits of data) (Chapter 22.2.7.3), but when looking at the Parity Ram with a debugger it looks like there is only 1 Parity for a 32bit word. Is this an error in the reference Manual?
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Forum Post: RE: MSP430FG4618: High frequency oscillator (7.3728MHz) on XIN/XOUT is not oscillating
Hi Evan, Thank you for your prompt response. We will try the approaches you've suggested. With regards to your question: [quote userid="416841" url="~/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1108308/msp430fg4618-high-frequency-oscillator-7-3728mhz-on-xin-xout-is-not-oscillating/4107050#4107050"] Is there a reason you can't use XT2 to drive the xtal? Just trying to brainstorm some options. [/quote] We're currently updating an old hardware design to use new parts and add some additional features to our hardwre and software. In our old hardware design (let's call it HW 1.0) we had only one crystal (the 7.3 MHz crystal) that was connected to XT2 to be used as main clock source for both MCLK and SMCLK. XT1 wasn't used at all, so the pins for XT1 weren't connected at all. However, our software had to continually monitor and clear the OFIFG flag until the clock signal became stable: do { IFG1 &= ~OFIFG; for (i = 50000; i; i--); } while (IFG1 & OFIFG); When we made the first prototype of our new hardware design (let's call it HW 2.0), we kept the 7.3 MHz connected to XT2, but our software never went out of this loop, because OFIFG remained active forever. That's when we saw that the data sheet had been updated after our HW 1.0 was made. The latest version of the MSP430x4xx Family User's Guide (Rev. L) says in section 5.2.4 (on page 5-10 / 296 in the PDF file): If there is only one crystal in the system it should be connected to LFXT1. Using only XT2 causes the LFOF fault flag to remain set, not allowing for the OFIFG to ever be cleared. That's when we decided to make a new version of our prototype (let's call it HW 2.1) where we connected our 7.3 MHz crystal to XT1 and left XT2 unconnected. We thought that our crystal didn't work at XT2 because there wasn't a crystal on XT1, but now I'm wondering: is it possible that the fact that the crystal didn't work on XT2 wasn't caused by XT1 being empty, but rather because XOSC8 or a similar issue arises on XT2 as well? Regards, Jonan
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Forum Post: TMS320F28379D: Dual Core Startup delay issue
Part Number: TMS320F28379D Hello there! I have an issue with F28379D MCU. The problem is about CPU1 and CPU2 communication. I am sending you programs for both cores (see below). Program is very simple (in the code, there are comments in Czech language, you can ignore them), CPU1 asks CPU2 for data, CPU2 place them into message ram and CPU1 print them via UART. It works properly if there is delay in form of for loop on line 40, but If I delete it, then UART output sends a random data garbage with random length. I do not know, why the delay is so crucial. I added conditions asking for boot state of CPU2, cleared FLAGS 32 and 0, but no change. Only change is the delay (the delay time is randomly set by me, probably it can be shorter). The easies way for you to see the problem is to load it to F28379D launchpad and see the difference when the delay for loop on line 40 is there or is commented out. You should see the behavior when you connect COM terminal to the device. Please, could you give me an advice, why it behaves like that and how to resolve it, so I will not use random delay in the code? Thank you very much for help. Vojtech Skrivanek MainCPU1.c : // Included Files #include "F2837xD_Ipc_drivers.h" #include "pin_map.h" #include "sci.h" #include "gpio.h" void Cpu2Start() { // cekej, dokud neni CPU2 spusteno (referencni manual kap. 4.10.11.3) while ((IpcRegs.IPCBOOTSTS & C2_BOOTROM_BOOTSTS_SYSTEM_READY) != C2_BOOTROM_BOOTSTS_SYSTEM_READY); // cekej, dokud nejsou CPU2 IPC priznaky 0 a 31 dostupne while ((IpcRegs.IPCFLG.bit.IPC0 == 1U) && (IpcRegs.IPCFLG.bit.IPC31 == 1U)); // nastaveni startovaciho rezimu CPU2 (referencni manual kap. 4.10.8.2) IpcRegs.IPCBOOTMODE = C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH; // prikaz na provedeni noveho startu programu CPU2 (referencni manual kap. 4.10.8.2) IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; // nastaveni priznaku, aby CPU2 provedlo prikaz (referencni manual kap. 4.10.8.1 a // TMS320F2838x Real-Time Microcontrollers With Connectivity Manager kap. 5.5.2 a 5.7.2 IpcRegs.IPCSET.all = 0x80000001U; } // Main void main(void) { Cpu2Start(); // povoli hodinovy signal pro SCIA EALLOW; CpuSysRegs.PCLKCR7.bit.SCI_A = 1U; EDIS; // nastavi GPIO 42/43 jako TX a RX pro UART GPIO_setPinConfig(GPIO_42_SCITXDA); GPIO_setPinConfig(GPIO_43_SCIRXDA); for(int x = 0U; x < 20000U; x++); // vstupni frekvence je f_intosc2 (10 MHz) / LSPCLK (4) = 2,5 MHz SCI_setConfig(SCIA_BASE, 2500000U, 9600U, (SCI_CONFIG_WLEN_8 | SCI_CONFIG_STOP_ONE)); uint8_t* messageRamIn = (uint8_t*)0x03F800U; // posli preruseni 0 pro CPU2 IpcRegs.IPCSET.bit.IPC0 = 1U; // cekej na potvrzeni od CPU2 while(IpcRegs.IPCFLG.bit.IPC0 == 1U); // odesli data o dane delce z RAM SCI_writeCharArray(SCIA_BASE, &messageRamIn[IpcRegs.IPCRECVADDR], IpcRegs.IPCREMOTEREPLY); // Loop Forever for(;;) {} } MainCPU2.c : // Included Files #include "F2837xD_Ipc_drivers.h" #include "hw_ints.h" #include "interrupt.h" #include "stdio.h" #include "string.h" // ukazatel na zacatek message RAM uint8_t* messageRamOut = (uint8_t*)0x03F800U; // data const char data[] = "Data prenesena z CPU2 do CPU1 pomoci Message RAM"; __interrupt void IPC_ISR0() { uint8_t datovyPosun = 15U; memcpy(&messageRamOut[datovyPosun], data, strlen(data)); IpcRegs.IPCSENDADDR = datovyPosun; IpcRegs.IPCLOCALREPLY = strlen(data); // vynuluj priznak preruseni IpcRegs.IPCACK.bit.IPC0 = 1U; // vymaze priznak preruseni skupiny 1 Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1); } // Main void main(void) { // globalne vypne preruseni jadra DINT; // Incializuje radic preruseni Interrupt_initModule(); // povoli linku 1 preruseni jadra Interrupt_enableInCPU(INTERRUPT_CPU_INT1); // povoli preruseni IPC_0 Interrupt_enable(INT_IPC_0); // zaregistruje funkci do vektoru preruseni pro IPC_0 Interrupt_register(INT_IPC_0, IPC_ISR0); // globalne povoli preruseni jadra EINT; // Loop Forever for(;;) { } }
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Forum Post: TMS320F28023: SFRA lib
Part Number: TMS320F28023 Other Parts Discussed in Thread: SFRA Hello, can customer migrate the SFRA lib on the F28023? Is the memory size ok? Is floating point needed? Do you have an app note if customer can't use the SFRA and have to measure analog with an frequency analyser? Regards, Holger
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Forum Post: LAUNCHXL-F28069M: About user.h setting problem
Part Number: LAUNCHXL-F28069M Dear Yanming Luo： Thanks for your previous help! I still want to consult about the settings of user.h. Although I have checked the TI related files, I still do not understand the understanding of USER_IQ_FULL_SCALE_CURRENT_A/USER_IQ_FULL_SCALE_VOLTAGE_V, which may be the reason why my motor control theory is not good. My understanding is that these two parameters have no absolute relationship with the hardware, but they cannot be greater than USER_ADC_FULL_SCALE_CURRENT_A /USER_ADC_FULL_SCALE_VOLTAGE_V (these two parameters are determined by the hardware), this can be referenced from the instaSPIN-FOC user's Guide, but from the routine It can be larger than the value of USER_ADC_FULL...., especially USER_IQ_FULL_SCALE_VOLTAGE_V. Why do I say this, because when I tested my project, I found that the value displayed by gMotorVars.Vs was beyond my imagination. Bemf could not be so high. I understand that Vs should be the scalar value of the motor phase voltage. My motor is AC three Phase 220V, bus voltage 315V, gMotorVars.Vs reached over 500V at 1400rpm, and I set USER_IQ_FULL_SCALE_VOLTAGE_V = 450V. Therefore, how should I set these two parameters USER_IQ_FULL_SCALE_CURRENT_A/USER_IQ_FULL_SCALE_VOLTAGE_V? I hope to get your help! best regard! Quan
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Forum Post: RE: AM2732: How to build cascade appimage
Hi, The below makefile should help you to get the appimage generated. So if you replace the makefile in SDK application with this makefile, the file will generate the appimage. e2e.ti.com/.../makefile Let me please know if you have any questions. Thanks and Regards, Akshay.
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Forum Post: TMS320F28335: Not able to change the EPOCH from 1900 to 1970 for the localtime function (time.h)
Part Number: TMS320F28335 Hi, I am using localtime inbuilt function to convert Unix time stamp into tm structure. As written in the thread " https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/493367/c2000-cgt-15-x-y-time-h-changes/1785188?tisearch=e2e-sitesearch&keymatch=c2000%252520localtime#1785188 the EPOCH can be changed from 1900 to 1970 by defining "-D__TI_TIME_USES_64". This is somehow not working for my setup: Compiler: 21.6.0.LTS SYS/BIOS: 6.83.0.18 When I pass the value "1456822873ULL" (should be Tue Mar 01 2016 09:01:13 GMT+0000) to the function "localtime" of "time.h" I get the value "116" for the variable "tm_year" in the tm structure. I expect the value "46" because of the EPOCH 1970. I have defined "-D__TI_TIME_USES_64". Thanks in advance for your support! Regards, Matthias
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Forum Post: RE: TMS570LC4357: FreeRTOS
1) The FIQ and IRQ are disabled by default, why the F and I bits are cleared in your snapshot. The default mode should be supervisor mode (M[4:1]=b10011), why is it user mode (b10000) in your snapshot? Ans) I am not sure why. 2) Did you call other function before calling _coreInitRegisters_()? Ans) No I have not added anything before the _coreinitRegisters(). 3) Can you reset the device (using CCS-->Run-->Reset-->System reset), then check if CPSR restores its default value? Its default value is 0x000003D3. Ans) I did this and observed that the correct sequence of Mode change happens in case of (using CCS-->Run-->Reset-->System reset) and (using CCS-->Run-->Reset-->CPU reset) but in the case of the Restart button. My Observation: - 1. using CCS-->Run-->Reset-->System reset = Tasks are running fine by triggering the Preemptive ISR. Mode is System Mode while at FPU enable Instructions in _coreinitRegisters_(). 2. using CCS-->Run-->Reset-->CPU reset = Tasks are running fine by triggering the Preemptive ISR. Mode is System Mode while at FPU enable Instructions in _coreinitRegisters_(). 3. Restart = undef Abort at FPU Enable instructions in _coreinitRegisters_() because of accessing CP15 registers in User Mode. Thank You.
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Forum Post: TMS570LC4357: Is it possible to use the two pins of I2C1 on the LAUNCHPAD XL2 development board to communicate directly with other I2C devices?
Part Number: TMS570LC4357 Other Parts Discussed in Thread: HALCOGEN Hi team, Here's an issue from the customer may need your help: Using the LAUNCHXL2 570LC43 development board, the customer attempts to communicate with I2C devices on other boards using the two pins of I2C1 that are brought out on the board. J2 numbers 1 (GND) 8 and 9 are used in the figure below and are connected to the GND and I2C pins on the other boards, respectively. HALCoGen configuration is as follows: The customer calls the i2cInit() function in the main function and tries to communicate with the device, but the program is stuck in the i2cIsMasterReady or i2cSendByte function. Grabbed both pins with an oscilloscope and did not see any waveforms. Can it be connected directly like this? Could you help check this case? Thanks. Best Regards, Cherry
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Forum Post: TMS320F280049: Clear the TripZone interrupt flag bit
Part Number: TMS320F280049 Hi team, Here's an issue from the customer may need your help: The current program's TripZone related configuration is as follows: The CTRIPH signal from the comparator is output to XBAR_TRIP4. Then DigitalCompare, which takes 4 PWMs, is the source for one-shot-trip. The DCA_Event / DCB_Event output signal then sources TripZone. When actually running, after the comparator is triggered, it goes into PWM1's TripZone interrupt ISR, then immediately disable ePWM TipZone Interrupt, and clear CMPHSTS, TZFLG, and TZOSTFLG. However, when ePWM TipZone Interrupt is re-enabled after the actual fault is removed, the trip Zone interrupt ISR for the remaining 3 PWMs is again entered. What more flags need to be cleared to allow it to not enter an interrupt when re-enabled? Thanks. Best Regards, Cherry
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Forum Post: RE: TMS320F280049C: EPWMxA and EPWMxB simultaneously generate high-precision PWM waves
Hi, Thanks for your help. [quote userid="280106" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1108152/tms320f280049c-epwmxa-and-epwmxb-simultaneously-generate-high-precision-pwm-waves/4106736#4106736"]So you can set the CMPBHR to the same value as CMPAHR.[/quote] So does that mean high precision PWM waves for EPWM1B channel be achieved with CMPA+CMPBHR (CMPBHR set to same value for CMPAHR)? Thanks and regards, Cherry
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Forum Post: TMS320F28035: C2Prog burning 28035 problem
Part Number: TMS320F28035 Hi When we use C2PROG 1.8.11-7 to record the software, the software show No Response But through this SCI interface, normal communicating packets had no problem We confirmed that the 28035 has be in Boot Mode The waveform of the actual measurement of SCI in 28035 pin is as follows 28035 RX input pin (YELLO) 28035 had no response in Tx output pin(Blue) Is there any point to confirm to solve this problem? The architecture is as follows Thanks
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Forum Post: RE: UNIFLASH: UNIFLASH
Hi Jackson, yes - do always ask, please! We must be down to the level of being something trivial and obvious & thereby very difficult to find ... and all you have to go on to help me is what I send, so I'm always happy to add info. And, as I've made my s/w show me what its doing for debug already, it's only a matter of running it and copying out the relevant bits. To which - I've got the OPEN (includes length), SEND for the last chunck ... includes chunk length and/or not the checkSum, and CLOSE for all combinations. Well, I haven't included the with-checkSum FLASH version ... its exactly like the SRAM one but with the code changed (26 > 24), and works. I've also included what I've done to your pythons - which also does not work. SRAM no checkSum: commandNumber: 3: {Open to Sram} metaImage number: 1 metaImage type:4 1347: {Write to Sram} metaImage number: 1 metaImage type: 4 chunk: 1342 Remainder bin file addr: 0004EA20 : : : : : : 1348: {Close to Sram} SRAM with checkSum: commandNumber: 3: {Open to Sram} metaImage number: 1 metaImage type:4 1347: {Write to Sram} metaImage number: 1 metaImage type: 4 chunk: 1342 Remainder bin file addr: 0004EA20 : : : : : : 1348: {Close to Sram} FLASH, no checkSum commandNumber: 4: {Open to Flash} metaImage number: 1 metaImage type:4 1348: {Write to Flash} metaImage number: 1 metaImage type: 4 chunk: 1342 Remainder bin file addr: 0004EA20 : : : : : : 1349: {Close to Flash} and the reply was: 1348: {Write to Flash} metaImage number: 1 metaImage type: 4 chunk: 1342 Remainder rxLength: 5 bytes commandNumber: 1349: {Close to Flash} rxLength: 5 bytes NACK? says it's failed? Yes, no response in SOP4 ... and red led lit. I'm pressing the NSRT (SW2) button between each trial - and sending BREAK to open the comms. What have I done to python to make it SRAM (UNIFLASH 6.4.0)... #propertiesMap['COMPort'] = 'COM37' propertiesMap['COMPort'] = 'COM4' #propertiesMap['MemSelectRadio'] = 'SFLASH' propertiesMap['MemSelectRadio'] = 'SRAM' #propertiesMap['DownloadFormat'] = True def _send_start_download(self,file_id,file_size,max_size,mirror_enabled,storage): storage="SRAM" def download_file(self,filename,file_id,mirror_enabled,max_size,storage, imageProgList): storage="SRAM" CLOSE not changed - it send metaImage ID, not storage type This does NOT work i.e. send, then try to talk to com port - no reply. Hope that's everything you asked for... thanks Alan
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Forum Post: TM4C1294KCPDT: WatchDog timer -TM4c1294KCPDT
Part Number: TM4C1294KCPDT Hi, In my coustom board using TM4C1294KCPDT controller , in that i need to enable watchdog timer for my application. I am following TI Example Watchdog timer code ,interrupt is generating every one second once. Problem is when i am pusing the variable g_bFeedWatchdog as " Zero " Controller doesn't get reset instead of that its show " Device is locked up in Hardware fault " . Below i have attached fault screenshot as well as code for your refernce . Please let me know if did any mistake in coding ? Regards, Rani volatile bool g_bFeedWatchdog = true; void WatchdogIntHandler(void) { // // If we have been told to stop feeding the watchdog, return immediately // without clearing the interrupt. This will cause the system to reset // next time the watchdog interrupt fires. // if(!g_bFeedWatchdog) { return; } // // Clear the watchdog interrupt. // MAP_WatchdogIntClear(WATCHDOG0_BASE); // // Invert the GPIO PN0 value. // } void watch_dog() { // // Enable the peripherals used by this example. // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION); // // Enable processor interrupts. // MAP_IntMasterEnable(); // // Set GPIO PN0 as an output. This drives an LED on the board that will // toggle when a watchdog interrupt is processed. // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0); // // Enable the watchdog interrupt. // MAP_IntEnable(INT_WATCHDOG); // // Set the period of the watchdog timer to 1 second. // MAP_WatchdogReloadSet(WATCHDOG0_BASE, (g_ui32SysClock)); // // Enable reset generation from the watchdog timer. // MAP_WatchdogResetEnable(WATCHDOG0_BASE); // // Enable the watchdog timer. // MAP_WatchdogEnable(WATCHDOG0_BASE); }
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Forum Post: TMS320F280039C: CLB exectue speed
Part Number: TMS320F280039C Other Parts Discussed in Thread: TMS320F280049C Hi Experts, Our project try to move to TMS320F280039C from TMS320F280049C. We start to check major the functions using LaunchPad Kit(F28003X). When evaluating the CLB module, the application behavior of the CLB fucntion is correct and the task time consumption is much better than TMS320F280049C. We check all the CLB functions of TMS320F280039C are executed faster than CLB of TMS320F280049C. For example, the CLB reset function will consume 20us for 49C but only 5us for 39C. We know the 39C are improved the +20% for CPU speed (120Mhz). But the time consumption is 4X decrease. Is it correct for CLB time behavior? Thanks Casper
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Forum Post: RE: TMS320F28388D: CPU2, CM firmware update using CPU1
Actually, I'm also looking F2838x SCI flash kernel example. I think I should use this example. Thanks for letting me know.
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