Part Number: TM4C129XNCZAD Good day, We refer to the "USB Serial Device Firmware Upgrade" to try to build the bootloader, /cfs-file/__key/communityserver-discussions-components-files/908/USB_5F00_Serial_5F00_DFU.pdf except for modifying the chip type to fit our board (TMC4129), all other steps are done according to the manual instructions, and encountered a problem with the USB device not being recognized. We don't know where the problem is, please give me advice, thanks. e2e.ti.com/.../bootloaderusb_5F00_10Jun2022.zip Ray Yang
↧
Forum Post: TM4C129XNCZAD: DFU enumeration failure with TM4C129
↧
Forum Post: RE: TM4C129XNCZAD: DFU enumeration failure with TM4C129
Reference the part 2 regarding the document, Build the TivaWare boot loader. Ray Yang
↧
↧
Forum Post: RE: TM4C129XNCZAD: Update the firmware failed by ROM_UpdateUSB()
Hi , This project uses TI RTOS, the timer is already occupied by the RTOS. Currently trying to use the flash base bootloader to solve the problem, but the progress is not very smooth. Ray Yang
↧
Forum Post: RE: RM42L432: Download and run code direct from RAM, can't reach the main procedure
Hi QJ, and what is the difference in compare with my linker command file posted at the start? I call it RAM, you call the memory FLASH0. Without defining the "FLASH0" memory it doesn´t make any sense... So, what is the "MEMORY" definition of your FLASH0?
↧
Forum Post: RE: TMS320F280039C: __TI_resource_lock(__TI_LOCK_DEVICE_TBL) Causes Illegal Operation
Can you also share the snapshot of core registers just after the LCR __system_pre_init statement? Regards, Veena
↧
↧
Forum Post: RE: TMDSCNCD28379D: TMDSCNCD28379D
Dear Omer, Thank you so much. without this doc, it was impossible to continue working on Delfino. I really appreciate it. I wanna ask you the last thing. I wonder if I can find the SCH of the "controlcard docking station R6" or "TMDSHSECDOCK". Sincerely Farzaneh
↧
Forum Post: RE: AM2634-Q1: Can QSPI memory-map reads external Flash in 16/32 or even 64-bit?
Hi Daniel, I wrote a program to test the 32-bit access to external Flash as below: // QSPI configuration CSL_QspiRegs * qspi_regs_struct = (CSL_QspiRegs *)CSL_QSPI0_U_BASE ; qspi_regs_struct->SPI_SWITCH_REG = CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_CFG_PORT ; // configure SPI_CORE // SPI Clock generator qspi_regs_struct->SPI_CLOCK_CNTRL_REG = (qspi_regs_struct->SPI_CLOCK_CNTRL_REG & (~CSL_QSPI_SPI_CLOCK_CNTRL_REG_DCLK_DIV_MASK)) | 0U ; // 80 MHz qspi_regs_struct->SPI_CLOCK_CNTRL_REG |= CSL_QSPI_SPI_CLOCK_CNTRL_REG_CLKEN_MASK ; // SPI Clock polarity and phase modes 3 (or 0) qspi_regs_struct->SPI_DC_REG = qspi_regs_struct->SPI_DC_REG | CSL_QSPI_SPI_DC_REG_CKP0_MASK | CSL_QSPI_SPI_DC_REG_CKPH0_MASK ; // SFI configuration qspi_regs_struct->SPI_SETUP0_REG = (CSL_QSPI_SPI_SETUP0_REG_RCMD_MASK & 0x6CU) | (0x3U SPI_SWITCH_REG = CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_MM_PORT ; readFlash = *((uint32_t *)0x60000000) ; And from the waveform of QSPI interface, it can directly read a 32-bit word for one transaction. And I think 32-bit read will help speed up the SBL boot time. MCU+ SDK is copying data in byte, which is slower. I am not sure what is the width of the DMA case, please help confirm if it is 8-bit width too. Could BU help modify the driver to support 32-bit or 16-bit access to external Flash device? It will help my customer to meet their OEM's requirement. Thanks a lot. Best Regards, Will
↧
Forum Post: TMS570LS1227: TMS570LS1227: F021 v02.01.01 API causes prefetch abort
Part Number: TMS570LS1227 Hi All, I am using flash Api V2.01.0 of TI for TMS570LS1227. I am sharing with you my codes snip that fall the infinite loop. I saw two different mistake at code. When I push directly “Play” button at Debug Mode, code is run into Fapi_BlockErase function(at F_Api_2.PNG) and code goes to infinite loop at line 201(Picture BlockEraseFuntion) but when i paused the debug, it fall prefetch abort page. However if I use it with “StepOver” button step by step I can pass the BlockErase function and code can erease the flash banks after that it run into infinite loop at line 439 Fapi_Issue_ProgrammingCommand function (Picture F_Api_1) at debug mode. Then I stopped the code and saw my two byte data on flash memory at debug mode. Also I am using three different disable Interrupt functions ( _disable_interrupt_() / _disable_IRQ_interrupt_() / _disable_FIQ_interrupt_() ) before go in to fapi functions. Can you offer different things about this and do you have flash programming code example for TMS570LS1227 ?
↧
Forum Post: RE: RM48L952: Error handling for DCAN RX over DMA
I have problems receiving, not transmitting. And I use FIFO for RX messages. Not for particular ID, but for any ID. I don't know IDs in advance.
↧
↧
Forum Post: MSP432E401Y: Unable to publish data more than 1024 bytes using NO-RTOS lwip mqtt
Part Number: MSP432E401Y Hello, I am using MSP432E401Y for implementing cloud based IoT data logging. I have used "simplelink_msp432e4_sdk_3_10_00_11" sdk in NO-RTOS mode and used its mbedtls library with lwip+mqtt. I have successfully connected and published data upto 1000bytes to secure mqtt broker (viz. AWS/ Mosquitto, etc.). But when my data length goes beyond 1024 bytes, then while trying to publish data, it won't get received on broker; instead my connection with broker got disconnected. In mqtt library file, 'mqtt_recv_callback' function called with null pbuf which indicates connection is disconnected when I try to publish more than 1024bytes data. Observations: 1. Data gets published to any mqtt broker successfully if length of the data is less than 1024 byes 2. I tried to publish data of length 2048 bytes using third party mqtt client viz. 'MQTT_BOX' on both AWS & Mosquitto secure broker and it got published successfully. (i.e. No error on broker side) 3. In lwipopts.h file I have set macros as: #define TCP_WND 4096, #define TCP_MSS 4096 4. In mqtt_opt.h file macro set as: #define MQTT_OUTPUT_RINGBUF_SIZE 5120 5. Below is the wireshark log where yellow highlighted row indicates the data being published by device (using lwip mqtt file) to secure mosquitto broker. But the broker sends disconnect i.e. (FIN,ACK) in response. 6. Below wireshark screenshot shows data being published successfully when its length is less than 1024 bytes (note highlighted yellow marked lines) Kindly suggest some solution on this.
↧
Forum Post: RE: TMS320F28388D: Illegal Mnemonic specified
Matthew, B instruction is used for looping not for jumping from one address to another address. I tried that but it is giving me below error: Thanks and regards, Pranay.
↧
Forum Post: RE: TMS320F280049C: I2C clarification requied
Hi Manoj, Its not i don't want to use fifo. Here am trying to understand how everything works . My understanding to use FIFO was to enable it, set the buffer level, set the interrupt isr ..but here u see in the example we are not doing any of this , we are just enabling fifo. i am looking to clear that specific doubt first. Thanks and regards, Stevin Martin
↧
Forum Post: RE: AM2634-Q1: Can QSPI memory-map reads external Flash in 16/32 or even 64-bit?
Hi Daniel, I have modified the SDK as follow: static int32_t QSPI_spiMemMapRead(QSPI_Handle handle) { /* Destination address */ uint32_t *pDst = NULL; /* Source address */ uint32_t *pSrc = NULL; /* Transaction length */ uint32_t count; /* Memory mapped command */ uint32_t mmapReadCmd; uintptr_t temp_addr; uintptr_t offset; int32_t status = SystemP_SUCCESS; uint32_t dummyBytes, dummyBits; if(handle != NULL) { QSPI_Attrs const *attrs = ((QSPI_Config *)handle)->attrs; QSPI_Object *object = ((QSPI_Config *)handle)->object; QSPI_Transaction *transaction = object->transaction; const CSL_QspiRegs *pReg = (const CSL_QspiRegs *)attrs->baseAddr; /* Get flash offset */ offset = (uintptr_t)transaction->addrOffset; /* Extract memory map mode read command */ mmapReadCmd = (uint32_t)object->readCmd; /* Set the number of address bytes */ CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_NUM_A_BYTES, (object->numAddrBytes - 1)); dummyBytes = object->numDummyBits / 8U; dummyBits = object->numDummyBits % 8U; CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_NUM_D_BITS, dummyBits); CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_NUM_D_BYTES, dummyBytes); CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_RCMD, mmapReadCmd); switch(object->rxLines) { case QSPI_RX_LINES_SINGLE: { CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_NORMAL); break; } case QSPI_RX_LINES_DUAL: { CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_DUAL); break; } case QSPI_RX_LINES_QUAD: { CSL_REG32_FINS((&pReg->SPI_SETUP0_REG)+(attrs->chipSelect * 0x4U), QSPI_SPI_SETUP0_REG_READ_TYPE, QSPI_MEM_MAP_READ_TYPE_QUAD); break; } default: break; } temp_addr = ((uintptr_t)attrs->memMapBaseAddr + (uintptr_t)transaction->addrOffset); pSrc = ((uint32_t *)(temp_addr)); pDst = (uint32_t *)transaction->buf; count = transaction->count; if (attrs->dmaEnable == true) { QSPI_edmaTransfer(pDst, pSrc, count, handle); } else { while(count > 0) { /* Do the normal memory to memory transfer. Copy will be in bytes */ *pDst = *pSrc; pDst++; pSrc++; count -= 4; } } } else { status = SystemP_FAILURE; } return status; } And I compared with the original one. The results are shown in following figures: (1) the original one: (2) the modified one: As you can see, the CPU load time is shorter. Best Regards, Will
↧
↧
Forum Post: RE: TMS320F28388D: Project rebuild works, symbols could not be resolved in shared header files
Hello Ki, in the meantime i closed an reopened all three project in CCS. After that somehow everything works fine. So thanks for your support. If the problem returns i will come back with a new post Kind regards Ralf
↧
Forum Post: RE: AM2634: The Expressions in the CCS Debug suffer "execution state prevented access"
Dear Ming, I understand, but XDS560 is too expensive. I think maybe TI engineers should make it possible to use those more affordable debug probes to display the expression values while the core is running. This is important when debugging the project. Like on C2000, we can do this even with XDS100. Best Regards, Jony
↧
Forum Post: RE: TMS320F28379D: Cannot Set HRPCTL.PWMSYNCSEL For non-HRPWM with DriverLib
Hi Marlyn, Thanks for the update and workaround but it doesn't work for ePWM9 to 12 due to point 2). But no matter, I've created my own EPWM_setSyncPulseSource() in my application code for now. Kier.
↧
Forum Post: TIDM-02010: Irms and Vrms value in Expression window
Part Number: TIDM-02010 While running the motor how to see the values of Vrms and I rms of motor 1 and Motor2 in expression window.
↧
↧
Forum Post: AM2434: Can CPSW and PRU-ICSSG Enet be used together?
Part Number: AM2434 Dear Champs, Is it possible to use Enet(CPSW) and Enet(ICSS) together? When my customer tried to make Enet(CPSW) and Enet(ICSS) to be active in syscfg together as below, they find errors caused by same name conflict in some variables and functions of 'tidrivers_config.c'. They enabled Enet(CPSW) and Enet(ICSS) together as below. The error was occurred in CCS as below. The generated ti_drivers_config.c file and syscfg file are in below. e2e.ti.com/.../ti_5F00_drivers_5F00_config.c e2e.ti.com/.../5633.example.syscfg Thanks and Best Regards, SI.
↧
Forum Post: RE: TMS320F280049C-Q1: tms320f280049c
Hi Navaneeth Narayansway we also stuck in EST_run,EST_getFm_lp_Hz,how we get definitions of this funtions or est.c file.
↧
Forum Post: RE: MCU-PLUS-SDK-AM243X: JavaScript Version of Scripting Console
Hi John Thanks for the response. I did a little bit of digging with your information and think ECMA Script Version 3 is then supported? https://www-archive.mozilla.org/js/language/E262-3.pdf Can you confirm this? Thanks! Fabian
↧