Hi Dennis, thanks for asking, unfortunately there is no change on that issue. I can program a new MSP430 chip for the very first time but re-programming, verify, read or erase it, is not possible. I was able to do all this with the MSP-FET programmer without any issue, and after erase the device with MSP-FET, I was able to program the same MSP again with the MSP-GANG programmer. Without any change for the cabling, the device or the MSP430 chip. With best regards Rolf
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Forum Post: RE: MSP-GANG: Support request, MSP-GANG programming - Error 23: MCU device initialization
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Forum Post: AM2432: SPI INTERFACE
Part Number: AM2432 Hi, I am planning to use 5/7 MCSPI interfaces available in AM2432. I have a some doubts in the implementation What is the maximum speed I can use in SPI Interface? Can I work with 50MHz speed in all channels simultaneously? Is it possible to mix "MCU" and "MAIN" MCSPI, and both works at max speed at same time? Regards Athuljith R
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Forum Post: AM2432: GPIOs
Part Number: AM2432 Hi, I have some doubts on GPIOs of AM2432 How many GPIOs can we defined as interrupts? Can we hard code GPIOs as interrupts? How the Priority of interrupts can be defined? How fast a general GPIO can switch? Regards Athuljith R
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Forum Post: RE: TMS320F280049: IQmath configuration in the linker command file
Hi Shantanu, thank you for your answer but I don't understand it. In C2000ware (v4.00.00.00) are the linker command files "28004x_iqmath_flash_lnk.cmd" and "28004x_iqmath_ram_lnk.cmd". The path is: "..\device_support\f28004x\common\cmd". In these files I find the definitions for the sections "IQmath" and "IQmathTables". The definition of the section "IQmathTablesRam" is missing in both files. Please tell me what I have to enter for "IQmathTablesRam" for FLASH and for RAM applications. Regards, Jan
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Forum Post: RE: TMS320F280049: Unbonded Pins
Hi Nima, thank you very much for your answer. If this function is not available for the F28004x, I need information what to do with the unbonded pins. I want to use a 100-pin and a 64-pin device. What are the unbonded pins of these devices and what do I have to do with them? Regards, Jan
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Forum Post: RE: MSP430FR2476: msp430fr2476
David I have try again this morning the followig combination without succes, when is enable the I2c immediately is set the Busy Bit if during process before delete the bit #UCSWRST I delete the bit UCMODE_3 the bit Busy is not set. this procedure is also put immediately under the pinout configuration so no other configuration are enabled main_program: movx.w #STACK_POINTER,SP mov.w #(FRCTLPW+NWAITS_1),FRCTL0 mov.w #(FRWPPW+DFWP+PFWP),SYSCFG0 mov.b #10000000b,P1OUT mov.b #00000000b,P2OUT mov.b #00000010b,P3OUT mov.b #00000101b,P4OUT mov.b #10000110b,P5OUT mov.b #00000000b,P6OUT mov.b #11111111b,P1DIR mov.b #11111111b,P2DIR mov.b #11111111b,P3DIR mov.b #11011010b,P4DIR mov.b #01111111b,P5DIR mov.b #11111111b,P6DIR bis.w #UCSWRST,UCB1CTLW0 bis.w #(UCMODE_3+UCMST+UCSYNC),UCB1CTLW0_H bis.w #(UCSSEL0+UCSSEL1),UCB1CTLW0_L mov.w #160,UCB1BRW bis.b #(SCL+SDA),P4SEL0 bic.w #UCSWRST,UCB1CTLW0 bis.w #UCSWRST,UCB1CTLW0 bis.b #(UCMODE_3+UCMST+UCSYNC),UCB1CTLW0_H bis.b #(UCSSEL0+UCSSEL1),UCB1CTLW0_L mov.w #160,UCB1BRW bis.b #(SCL+SDA),P4SEL0 bic.w #UCSWRST,UCB1CTLW0 bis.b #UCSWRST,UCB1CTLW0_L bis.b #(UCMODE_3+UCMST+UCSYNC),UCB1CTLW0_H bis.b #(UCSSEL0+UCSSEL1),UCB1CTLW0_L mov.w #160,UCB1BRW bis.b #(SCL+SDA),P4SEL0 bic.b #UCSWRST,UCB1CTLW0_L Luigi
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Forum Post: RE: TM4C1290NCZAD: Porting the CDC Serial USB Communication example from the EK-TM4C1294NCPDT chip
Hi Ralph, thank you very much for your quick anwer. I tried also this example project but it results the same way that the PC says that I have an unkown usb device and the descriptor reqest failed. I took the example project changed the cpu from 129x to 1290NCZAD and removed the initialization of the LCD and also the pin configurations that I dont need just the USB pins were configured. The compiler was now a way never one. The original was compiled with the 5.2.6 and for the 1290 I had to choose the 20.2.6. I dont know if that could be a problem. Best Regards Gergely
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Forum Post: RE: RM42L432: Configure the registers of CAN's library
Thanks for you answer, Can I configure messageBOX1 on TX and RX directly on CAN's register ? and How ? Regard, Matheo
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Forum Post: RE: TMS320F28055: Programming Issue
Hi Marlyn, Now scan succeeded. The status msg as below. ------------------------------------------------------------------------------------------------- [Start: Texas Instruments XDS2xx USB Debug Probe_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ C:\Users\chand\AppData\Local\TEXASI~1\CCS\ ccs1040\0\0\BrdDat\testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 560/2xx-class product. This utility will load the program 'xds2xxu.out'. The library build date was 'Jun 25 2021'. The library build time was '16:23:59'. The library package version is '9.4.0.00129'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '13' (0x0000000d). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- This emulator does not create a reset log-file. -----[Perform the Integrity scan-test on the JTAG IR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG IR Integrity scan-test has succeeded. -----[Perform the Integrity scan-test on the JTAG DR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG DR Integrity scan-test has succeeded. [End: Texas Instruments XDS2xx USB Debug Probe_0] ------------------------------------------------------------------------------------------- after uploading i am getting the below. error. what to do? -sudip
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Forum Post: TMS320F28379D: measuring Temperature using digital temperature sensor DS18b20
Part Number: TMS320F28379D Good day everyone, I am using DS18b20 digital temperature sensor for my Temperature measurement. Earlier I am using Arduino and one wire library. now I want to use C2000TMS320F2879D for the same purpsoe along with other sesnors. I want to know which pins i can use to connect digital temperature sensor and how to process it?
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Forum Post: TMS320F280049-Q1: Input pulse width 5ns
Part Number: TMS320F280049-Q1 Hi, With HRcap, pulse width can be measured in high resolution. I understood that. 1) Am I right? But at this point, a small detail caught my eye. Below is the screenshot I took from the "TMS320F28004x Microcontrollers datasheet" file. Here it shows the minimum input pulse width as 110ns. 2) So when there is a 5ns pulse to its input, will the TMS320F28004x ignore this pulse? Can't detect it? 3) I want to measure the width of a 5ns pulse. What do you recommend?
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Forum Post: RE: TMS320F28386D: Suspected bug in CLB generated code
Hi Peter, Yes it will work unless the disable function has been called. However, if it had been called before, then you would need to call the CLB_enableOutputMaskUpdates function before the CLB_setOutputMask one. That is why I am telling the generated code is incorrect/misleading and should be modified. I didn't experience it otherwise as I didn't take that part of the code in mine, I was just trying out to help you enhancing the product and fixing a tiny bug Regards, Clément
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Forum Post: TMS320F28374D: problems with TI design software TI System Configuration Tool
Part Number: TMS320F28374D Other Parts Discussed in Thread: TMS320F28388D , SYSCONFIG Hi Experts, I am posting this inquiry on the behalf of our customer. Kindly see the message below: "I am trying to configure pins of some of the MCU chips (TMS320F2837x or TMS320F2838x) picked up as candidates for the core of our new ECS modules, required by pending power converter control projects and some similar applications. At the final stage of the configuration process (regardless of S or D versions of previously mentioned MCU chips), i.e. after I have assigned most of the MCU subsystems to the available pins (of the 337pin package), when I try to add one more subsystem (either McBSP or I2C port) design software crashes reporting "Oh Snap! The last change caused an exception" message (see attached image). I double-checked few times, that all required pins at which those interfaces (e.g. either of ports I2C-A, I2CB, McBSP-A, McBSP-B etc.) are normally available, are still unassigned! Used SysCfg files, demonstrating this issue, are also attached to this message. The same EXCEPTIONall crash issue pops-out when using that "TI System Configuration Tool" software for the pin assignment of the F2838x MCU chips (also 337-pin package version). Besides, it would be nice to know if users should be afraid of the fact that there are separate Tool configuration options for single- and dual-core versions of F2837x microcontrollers (FS2837xS and F2837xD), while there is only one Tool configuration option for F2838x series of Delfino microcontrollers. P.S: There are still several other issues related to the concurrent usage of particular subsystems available within TMS320F28388D MCUs (but first things first...) Additionally, I wanted to point out that I appreciate "resource conflict" warnings, which occasionally occur when I try to combine other unsupported subsystem combinations (due to incompatible pin assignments)." Below is the screenshot of the error and the sysconfig files mentioned. Kindly have a look. e2e.ti.com/.../SysConfig_5F00_setups-_2800_1_2900_.zip Would you kindly help with this inquiry? Thank you. Regards, Marvin
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Forum Post: RE: Does the latest version of C2000 compiler is the best for us.
Hello Geroge Mock, Thank you for your answer :) Would you like to add more details about the performance and stabilities of each one, please? Thanks and regards, S.Tarik
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Forum Post: TMS320F280049C: ADC noise
Part Number: TMS320F280049C Other Parts Discussed in Thread: INA181 , TMS320F280049 Hi all I developed 3 phase PMSM motor control board using TMS320F280049CPM (64pin version) MCU, For phase current sensing i use INA181A2 current sense amplifier and for phase voltage sense i directly connect the divided voltage to the ADC input. Unfortunately during hardware verification, i find that the ADC noise is so big, below are the summary : 1. ADC connected to DC voltage , come from battery and divided by resistor and Cbucket for S/H purpose of SAR ADC, From around 200000 data, there are always 2 other unexpected value which have quite significant probability, The standard deviation is between 0.5 -1 depend on the C bucket value. 2. ADC connected to DC voltage but, now come from internal DAC, this experiment have similar result with no 1. 3. ADC connected to INA181A2 (biased by 1.65V from TMS320 DAC), which it's input differential filter is shorted together (assume no differential voltage will be developed), from TINA simulation, i expect there will be total noise around 1mV at 1MHz BW (only 1 bit error for 12bit 3.3V adc ref), but unfortunately i get 10 unexpected value, with standard deviation 2.26 from around 200,000 data. 4 ADC connected to TMS320 PGAOF and using it's internal R 200Ohm and external 150pF cap as RC bucket. PGA gain is set to 3x and input is connected to battery and divided by resistor. This time i even get more than 30 unexpected result, with standard deviation 4.9 from around 200,000 data. During this verification, to make sure no switching noise come from the buck converter, buck converter input from high voltage bus is left floating, so it will not work. MCU and INA181 are supplied by battery and LDO. As i know, i have tried to develop the PCB as ideal as possible (i provide the related PCB image in the attachment as well), by using solid ground plane, very close trace from INA181 to MCU, use shield ground trace for long trace. Decoupling cap as recommended by TMS320 and INA, and the placement are very close to them, only there is no antialiasing filter, after INA181, since it will add pole zero at the current loop control (there are no anti aliasing filter in tms320 launch board as well) Please refer to the attached file for more information of my experiment. Unfortunately, i can't compare this result with tms320f280049 launch board, since the MCU is damaged. I tried to order the MCU, but all store have no stock :( Please share your experience using this MCU ADC and INA181 in term of noise performance Thank you and best regards evan e2e.ti.com/.../TMS320F28004-ADC-noise-result.pdf
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Forum Post: RE: TMS320F28388D: CM blinking LED flash application does not boot from flash after flash_kernel download
Hello Vamsi, It works now that I added the ALIGN(16) to the CM linker command file for all flash-mapped sections. Thank you for you support!!! So that means that the 'flash_lernel' example project has a demand for the application to be 128-bit aligned, since otherwise the Flash API causes problems. I can imagine that I am not the only one who missed the ALIGN instructions in the linker command file, since certain example projects such as blinking LEDs come without that ALIGN instruction in the linker command file. Allow me to make a suggestion for the 'flash_kernel' project, which your colleagues may find interesting (I refer to the CM flash_kernel project): Let us assume that you are adding the following code... uint16_t addressAndLengthCompensation; // Check how much we are away from a 128-bit aligned address addressAndLengthCompensation = BlockHeader.DestAddr & 0x000000FFL; // Move destination address artificially to the next lower 128-bit aligned address BlockHeader.DestAddr -= addressAndLengthCompensation; // Increase block size by the number of bytes that we moved the address BlockHeader.BlockSize += addressAndLengthCompensation // Fill the array with 0xFF, which means let the flash untouched for(i=0; i<addressAndLengthCompensation;i++) { Buffer[i] = 0xFF; } ...at this place where the red arrow points to: From now on let the following three 'for(j = 0; .....)' loops start from 'addressAndLengthCompensation' like here: 'for(j = addressAndLengthCompensation;...) Furthermore clear the variable addressAndLengthCompensation after running for the 1st time at this place, which means that the variable 'addressAndLengthCompensation' has only for one time a value unequal 0: I did not verify my approach but I am sure you know what I am aiming for. With that kind of alignment correction code you will allow users to forget the ALIGN adjustments inside the application linker command file, which may reduce customer feedback on your side. It would be great if you could ask the flash_kernel experts to think about it, maybe they like the idea. Thanks, Inno
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Forum Post: RE: MSP432E401Y: Firmware Update through Ethernet
I have tried to follow this example, but I could get it to work with our custom board. Testing with the launchpad gave the same result, but after cleaning the flash with Uniflash it did work as described. The launchpad has a fixed mac address, how can I store a mac address after cleaning the flash in a custom board and before loading the bootloader with BSL-scripter?
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Forum Post: MSP430FR6007: eUSCI - UART mode - RX stop bits
Part Number: MSP430FR6007 Hi It seems the receiver of the eUSCI in UART mode requires the number of stop bits selected by UCSPB to receive correctly. Is this correct? It is not explicit described how the UCSPB setting influence TX and RX individually. The only reference between RX and stop bits we can find, is in the description of framing error: “Framing error UCFE A framing error occurs when a low stop bit is detected. When two stop bits are used, both stop bits are checked for framing error. When a framing error is detected, the UCFE bit is set.” So we can see from the UCFE whether or not the required number of stop bits was received. But we don’t need to handle framing error in our protocol. It has build in error detection, e.g. by CRC check. What we see is, that data transmitted with one stop bit is not received correctly. The first byte is received correctly, but the following ones are incorrect – in a way that could match a delayed reception out of sync. So it seems that the stop bit setting for the receiver part not only influences the framing error function, but also controls when the receiver is open for a new start edge. Our protocol specifies two stop bits for transmission. This is only specified to get extra margin for re-synchronization at the next start edge in the receiver. In the embedded devices we have used in the past (both TI’s and others), the receiver has always only required one stop bit, independent of the UART stop bit setting. E.g. in the USART peripheral of the MSP430x4xx family. Because our devices interface with a wide range of other devices (both our own and 3 rd party, and both embedded and generic devices), some of them only use one stop bit (by mistake or because it can’t be controlled in the specific device). We haven’t been able to control this – and didn’t wanted to, because it worked okay. If our device TX’s two stop bits and RX’s one stop bit, it can work with all other combinations of one and two stop bits. If our device TX’s two stop bits and requires two stop bits on RX, it can only work with combinations where the counter part TX’s two stop bits. We know the “always one RX stop bit” is “text book incorrect”. But in normal asynchronous communication, it can provide important flexibility and margin. In our case, we could theoretically try to force all the other devices to follow the protocol to the letter. But in reality, in many cases we need the backward compatibility because it shall work with exiting devices or with devices that can’t be changed (e.g. if our costumer has bought their own devices from a subcontractor that no longer exists). Is there anyway this could be changed in existing or upcoming TI devices or families? We suggest one of the following solutions: 1) The UART RX only checks one stop bit, independent of the UART stop bit setting. 2) The UART could receive a new start edge after maximum 1 stop bit, independent of the UART stop bit setting. 3) The stop bit setting in the UART is split into separate settings for RX and TX. On our current project, we have the possibility to use two separate eUSCI’s for TX and RX respectively with different stop bit settings. But it means that we will never be able to use the opposite part of each of these interfaces. In other products we will need more interfaces with this feature, than we can support with two eUSCI’s per interface. We really hope for a positive answer! /Mads
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Forum Post: MSP430FR5739: Bare die bond pad information for our mounting processes
Part Number: MSP430FR5739 Hello, I am interested in mounting a bare die MSP430FR5739CY . Unfortunately, there is no pad information given in the datasheet. Could you tell me: - bondpad metallization material - thickness of bondbpad - size and position of the bondpads? - thickness of die Thank you!
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Forum Post: Differences between MSP430 comparators (Comp_E, Comp_A+, Comp_A, Comp_B)
Hi Team, Can you please advise main differences of available comparators (Comp_E, Comp_A+, Comp_A, Comp_B) on MSP430? Thanks in advance Best Regards Furkan Sefiloglu
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