Hi Stefan, I'm still waiting for feedback from our USS team.
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Forum Post: RE: MSP430FR6047: EVM430-FR6047: DC offset voltage is to high, when a higher gain is selected
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Forum Post: RE: MSP432P411Y: LCD segment enable causes I2C failure
Hi Ron, Ok, it sounds like you have it working and moving forward with your project. I'll dig into the details and see if the errata should be expanded. I will mark this posting as RESOLVED, but if this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread is locked, please click the "Ask a related question" button, and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.
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Forum Post: RE: LAUNCHXL-F28379D: Porting SCIA Echo Loopback to RAM Management Example
Hi Krishna, as a matter of fact, I did not change much on the RAM_Management project except adding the SCI initialization from line 173 to 183 (10 lines of additional code) as follows : // Setup for SCIA GPIO_SetupPinMux(43, GPIO_MUX_CPU1, 15); GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL); GPIO_SetupPinMux(42, GPIO_MUX_CPU1, 15); GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC); scia_fifo_init(); // Initialize the SCI FIFO scia_echoback_init(); // Initialize SCI for echoback msg = "\r\n\n\nHello World!\0"; scia_msg(msg); By right, the SCI code has been configured for baudrate 115200 (SYSCLK = 200 MHz, LSPCLK = 50 MHz). Somehow after inserting the SCI code into RAM_Management project, the baudrate is no longer 115200. I believe this is not an issue of SCI module, but somehow the RAM_Management project changes either SYSCLK or LSPCLK frequency which I could not pin point which function or what has caused the clock frequency get changed.
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Forum Post: RE: TMS320F28388D: What is the maximum CLK for EMIF?
For SDRAM MAX CLK frq is 100MHz. ASRAM is asynchronous interface so there is no clock but SETUP/HOLD and STROBE timing which can be set as no of EMIF CLK cycle and EMIF CLK can be set to 200MHz max for that. Regards, Vivek Singh
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Forum Post: RE: MSP430FR2476: Tiny RAM
Hi Eddie, I believe the BSL guide is wrong. The linker script file matches the datasheet and I setup a simple code to read/write to tiny RAM and it works. I'll submit a correction to the BSL guide. Thanks for bringing this to our attention. Regarding if BSL clears tiny RAM, I'll have to get clarification on that one.
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Forum Post: RE: TMS570LC4357: How to store a variable while clearing the RAM memory
Than you Wang. I was considering option 2 as maybe the simplest. Just wondering if there are registers reserved for this kind of "user usage". I've seen that in other uC, even backed-up by the external battery. But you're right, we can use any register in an unused peripheral as long as it's clocked and does not change any behavior.
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Forum Post: RE: TMS320F280049: IQmath configuration in the linker command file
Hi Jan, In C2000ware, we have not provided the IQMath libraries for F28004x. But you can use the same configurations in the cmd files of other devices. You have to use IQMathTablesRam if you are using IQexp, IQasin and IQacos functions. Otherwise, you do not need to include it. F28004x does support IQMath. Let me know if you are facing any difficulty -Shantanu
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Forum Post: MSP430F5500: About the monitoring voltage of the VBUS terminal
Part Number: MSP430F5500 Please tell me about the interrupt voltage that occurs when the voltage input to the VBUS terminal of [MSP430F5500] changes. -When the voltage supplied to the VBUS terminal drops below what V, does a voltage drop interrupt occur? -When the voltage supplied to the VBUS terminal exceeds V, does a voltage recovery interrupt occur? -Does it have hysteresis for the voltage monitoring supplied to the VBUS terminal? In that case, please tell us about the interrupt conditions for the monitoring voltage.
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Forum Post: RE: TMS320F28388D: Which unit is faster
Hi, Please go through the benchmarks that we provide as part of our documentation of the IQMath and FPUFastRTS libraries. You can find these in c2000ware. There, you can find the correct cycle counts for each operation. For division, you can also consider the FASTINTDIV library. For example, for sine, IQmath (For Q = 29) Takes 46 cycles and sin from FPUFastRTS takes 38. For IQMath, the cycles will vary based on the GLOBAL_Q value. Also keep in mind the additional overhead of converting between float and IQ format. PLease go through the documentation and get back to me if you require any clarifications. -Shantanu
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Forum Post: TM4C1294NCPDT: I2C Bus stuck. Need switch from I2C to GPIO then back to I2C during runtime
Part Number: TM4C1294NCPDT Other Parts Discussed in Thread: TCA9535 Dear Support Team, We are using TM4C1294NCPDT as I2C Master to communicate with TCA9535(I2C IO Expander) Salve. We are getting into situation where I2C Bus gets stuck. To getting the bus "unstuck" We are toggling the clock line multiple (18) times before doing any I2C operation with the slave device to convince it that the last transaction is complete. We are following the sequence below disable I2C peripheral (SysCtlPeripheralDisable(I2C)), enable GPIO Peripheral (SysCtlPeripheralEnable(GPIO)), use SCL and SD as digital output, enable I2C peripheral (SysCtlPeripheralEnable(I2C) But still unable to establish the connection with I2C Slave TCA9535. What could be the reason? Can we switch from I2C to GPIO mode then back to I2C mode during run time ? What is the correct way of dong this? or Is there any other way to tackle this situation ? Thanks & Best Regards, Prashant Naik
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Forum Post: TMS320F28388D: Failed to read/write EMIF2_SDRAM.
Part Number: TMS320F28388D Other Parts Discussed in Thread: C2000WARE Please tell me about the setting of EMIF2_SDRAM. On TMS320F28388D, I'm trying to connect from CPU1 to SDRAM of EMIF2_CS0. The ASRAM side is not connected to anything. Pin layout is as follows. There is a design error and instead of EMIF2_CS0n, EMIF2_CS2n is connected to the CS of SDRAM. =============================== D0-D15 : GPIO 122-132,133-138 A0-A12 : GPIO 95,98-109 BA0,1 : GPIO 111,112 CAS : GPIO 113 RAS : GPIO 114 (none) CS0n : GPIO 115 CS2n : GPIO 116 SDCKE : GPIO 117 CLK : GPIO 118 WEN : GPIO 120 =============================== CS0n (GPIO115) is not used. CS2n (GPIO116) is changed to GPIO setting and used as "substitute of CS0n" in "fixed LOW state". In the above environment, the C2000ware test source, the In the above environment, if I change the C2000ware test source, "emif_ex6_16bit_sdram_nonfar", to the EMIF2 setting and run it, it stops responding while clearing the SDRAM buffer to 0. When I check the CCS memory browser, it says I'm trying to "change 0x900000**", but it's actually "changing 0x000000**". The only problem I can think of is a wiring error. Is it possible to use EMIF without CS0n connected? Or is there some other mistake? The SDRAM I am using is "W9825G6KH-Winbond". Thank you very much for your help.
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Forum Post: RE: TMS320F28379D: SCI flash programming on custom made hardware
Thanks Vamsi & Anu for your reply. I have followed the procedure as mentioned in the document. but in command terminal my screen is stuck on- Usually, how much time kernel downloading takes?
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Forum Post: RE: TMS320F28379D: Unable to load program in Flash on Custom Development Board.
Hi Nirav, Thanks for replying back. We are using LM1085 series regulator. These regulators have current rating of 3A. PFB Schematic Screenshot. Input 15V is fed through a DC Power source with output current rating 2A. Please let me know if you any waveforms or other information. Thanks and regards, Abhay
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Forum Post: RE: AM2432: AFDX Implementation
Hi Senthilkumar, Regarding 1, the answer is yes enet-lld has the support for raw layer 2 packets. we have enet_layer2_cpsw example for it. Regarding 2, the answer is yes too. There many timers can be used to generate 0.5ms for any of the 5 cores (5 R5F, 1 M4F) Best regards, Ming
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Forum Post: RE: TMS320F28379D: Unable to load program in Flash on Custom Development Board.
Hi Abhay, How are the boot mode pins configured? On a fresh device, using wait boot prevents the CPU from executing garbage from Flash/RAM (when there is no valid code in them). Can you try wait-boot configuration if not already? Thanks and regards, Vamsi
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Forum Post: RE: LAUNCHXL-F28379D: spi_ex3_external_loopback_FIFO_interrupts Connection Diagram
The comments in the example at the top of example file should have the connections. Did you check that out?
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Forum Post: RE: TMS320F28388D: Boot from Ethernet
Benito, There is no boot option from Ethernet . Ethernet is only accessible from the CM core and the Initial boot on Reset can only be through CPU1, with boot options specified in the TRM. Best Regards Siddharth
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Forum Post: AM2432: DDR4 Lowest Clock
Part Number: AM2432 Hi, One of my customers is asking for the DDR4 lowest clock frequency. They are currently using DDR2 at around 150MHz and was wondering if DDR4 could be lowered to this frequency. Best regards, Mari Tsunoda
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Forum Post: RE: TMDSEMU110-U: Connection Issue TMSF28075
We didn't buy the emulator from texas or one of your distributor. How we could change them. Moreover the problem seems to be present on all the new emulators (I tested two)
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Forum Post: RE: MSP430FR2476: msp430fr2476
Bruce The UCB0SDA/SCL is also on the P4.3 SCL and P4.4 SDA I'm using this port
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