Part Number: MSPM0G1519 Tool/software: Seem to run out of SRAM memory when using more than 64k. Do I have to do something special to use both banks ? Are they contiguous ? Using GCC. Regards Phil
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Forum Post: MSPM0G1519: Can't seem to use 128k SRAM ?
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Forum Post: RE: AM263P4: QSPI S25FL128S Flash writing trouble
Hi Jeeuk, [quote userid="473084" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1529411/am263p4-qspi-s25fl128s-flash-writing-trouble/5883099#5883099"] Then, I have new questions about OSPI boot of AM263P4. What is the region of 0x80000~0x80FFF in flash memory? When are the data of that region flashing and when are the data used? [/quote] This the OSPI PHY tuning data, you can read more about it here: www.ti.com/.../spract2.pdf
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Forum Post: RE: LP-AM261: Send an interrupt from ICSSM1_PRU_1 to R5_0
Hi Daniel, Did this help: e2e.ti.com/.../lp-am261-how-do-i-send-an-interrupt-from-cortex_r5_0-to-icssm1_pru1
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Forum Post: RE: LP-AM261: I having problems with PRUICSS_loadFirmware()
Hi Daniel, Allow me to get back on this thread by early next week.
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Forum Post: LP-MSPM0G3507: factory reset manual
Part Number: LP-MSPM0G3507 Tool/software: [6/20/2025, 5:37:25 PM] [INFO] CS_DAP_0: GEL Output: Initiating Device Factory Reset [6/20/2025, 5:37:25 PM] [ERROR] CS_DAP_0: Trouble Writing Register SECAP_TCR: (Error -2131 @ 0x20204) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.1.0.3372) [6/20/2025, 5:37:25 PM] [ERROR] CS_DAP_0: GEL: Error while executing GEL_DAPInit_SECAPCommand(): Target failed to write register SECAP_TCR at 'REG'::SECAP_TCR=command [mspm0_cs_dap_init.gel:234] at GEL_DAPInit_sendCommand('GEL'::gDAPSecAPCmd) [mspm0_cs_dap_init.gel:403] at GEL_DAPInit_SECAPCommand()
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Forum Post: AM2612: Require recommended Parts
Part Number: AM2612 Tool/software: .Hello, I require to identify the parts required for my below high level design. Let me know suitable automotive qualified parts for below: 1. Controller 2. USB DRP controller 3. Switch Preferred controllers with support of Wi-Fi dongles in market. Thanks, Nikunj
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Forum Post: RE: AM2432: MCAN with DMA
Hi Mari, [quote userid="499871" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1515075/am2432-mcan-with-dma/5882901#5882901"]So as I understand it, are they only supposed to change the source files and NOT the example files - is this correct?[/quote] That is correct. But after they add this change, they need to rebuild the library as well as the example. [quote userid="499871" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1515075/am2432-mcan-with-dma/5882901#5882901"]We have asked them to try porting the example-side files from SDK11.0 to SDK9.2 previously, so if they need to revert these changes we will need to let them know.[/quote] This patch needs to be applied on default 9.2 SDK, so they need to revert these changes. [quote userid="499871" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1515075/am2432-mcan-with-dma/5882901#5882901"]Also - do you have details of the original Jira issue details? It seems to me that the only change here is to increase the buffer size allocated for data. Was the original issue due to lack of buffer size?[/quote] There was no issue with the buffer size, the DMA header data needed in DMA mode was being written to a wrong address in the buffer (because of *((uint32_t*)(((uint32_t*)data)+4))) this was fixed by adding +1 instead of +4. Best Regards, Meet.
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Forum Post: RE: AM2432: Feature support check
Hi Zekun Bai , Thanks for your query, Will check on this and get back to you by next week. Regards Ashwani
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Forum Post: RE: MCU-PLUS-SDK-AM243X: susipcious created .text_tcm-section
Hi Felix, Thanks for your follow up. Yes, your assumption is correct. The linker places the section in the first sufficient and "usable" memory space defined by the MEMORY directive of the linker.cmd file. You can always verify this by playing around with the different regions defined within MEMORY and observing the generated map file to see where each section is allocated. Kind regards, Kamil
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Forum Post: RE: AM263P4-Q1: HS-SE device failure to access OCRAM banks 4/5
Apologies, I was confusing the R5F image to the HSM syscfg there. I can confirm the HSM image was original as in the SDK. I've also checked the permissions set on the default hsm image firewalls. In generated syscfg code, it seems the permissions for all L2OCRAM banks are correctly set for access from all cores: In the related post you pointed to a bug in gMpuFirewallConfig (in mpu_firewall_v0_cfg.c) where definitions for CSL_FW_L2OCRAM_BANKx_SLV_CFG_ADDR are not set for both banks 4 and bank5 of OCRAM. Have added definitions for bank 4 and 5, will generate a test build and report back.
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Forum Post: RE: MSPM0G1519: Can't seem to use 128k SRAM ?
The top of mspm0g3519.cmd says: /* * Note: SRAM on this device is continuous memory but partitioned in the * linker into two separate sections. This is to account for the upper 64kB * of SRAM being wiped out upon the device entering any low-power mode * stronger than SLEEP. Thus, it is up to the end-user to enable SRAM_BANK1 for * applications where the memory is considered lost outside of RUN and SLEEP Modes. */ If you don't plan to use the lower-power modes, I suppose you can combine the two banks (double the size of SRAM_BANK0, delete SRAM_BANK1). Otherwise you'll probably have to put any "expendable" variables in a separate section and put them ">SRAM_BANK1".
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Forum Post: RE: AM263P4: When the SWAP feature is enabled ,How can I use Flash operation APIs (Flash_read, Flash_write, etc.) in region A to manipulate data physically located in region B (e.g., at 0x60500000)?
Hi Mingzhe Dai, Another approach which can be considered is to set the boot seg and boot mask register as 0 (essentially disabling the translation). This can be done by calling FSS_addressBitMask() with mask and segment as 0. After performing write operation, bootseg can be configured back. Regards, Aswin
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Forum Post: RE: AM263P4-Q1: failed MCAN communication using SDK example(mcan_external_read_write)
Hi Sung-IL, Apologies for the delay. I do not have the hardware with me right now, but this is my SW configuration: PCAN config: Example config: No change. Using SDK out of box example. I will send you an image of my EVM on Monday to cross check. Thanks and Best Regards, Aswathi
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Forum Post: RE: AM2634: AM263x MCAN: How to configure to receive any standard ID in message RAM buffer?
Hi there, I have received your query. Please give me few days' time to try this out on my end and get back to you. Best Regards, Aswathi
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Forum Post: TMS320F28386D: Out GPIO as input x-bar
Part Number: TMS320F28386D Tool/software: Hello, I have a GPIO output driven by CPU1 and a GPIO driven by CPU2. I would like to output a AND of both any SW intervention. So I was wondering if I could do that using the CLB with the GPIO outputs redirected to the CLB inputs through the input X-BAR. Would that work out ? I believe so but I want to get a confirmation. Clément
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Forum Post: RE: TM4C129XNCZAD: UART 0
Hi, [quote userid="582531" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1530163/tm4c129xnczad-uart-0"]Not receiving data on it.[/quote] Does transmit work? Or both transmit and receive are failing. Please run the example C:\ti\TivaWare_C_Series-2.2.0.295\examples\boards\ek-tm4c1294xl\uart_echo This example will echo everything you type at the terminal, meaning what is typed will be received by the MCU and then the same message being transmitted back to the terminal through UART0. Make sure you have the same baudrate, number of stop bits and no parity on both side. The example uses 11520-1-N. Use a scope or logic analyzer to probe the UART0TX and UART0RX. If you see proper UART0TX waveform but no UART0RX then you need to investigate the other end of the communication. I don't know if your UART0 is talking to the PC or another component with a UART interface. If you are talking to a PC, you need to go through a USB to Serial adapter such as a FTDI chip.
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Forum Post: RE: AM2634: AM263x MCAN: How to configure to receive any standard ID in message RAM buffer?
Sure Awasthi R, But try to help me out as soon as possible, because I'm running out of time, have deadline for my project
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Forum Post: TMDSCNCD263P: EEPROM Contents As Delivered From TI
Part Number: TMDSCNCD263P Tool/software: Hello, As per the user guide, the AM263Px Control Card has a I2C based 1Mbit EEPROM (CAT23M01WI-GT3). I see that the board version is stored at offset 0x0022 as per board.c #define EEPROM_OFFSET_READ_PCB_REV (0x0022U) I want to keep this obviously but also want to write my own data without overwriting existing data. If there is anything else stored in the EEPROM by TI, is there a document mentioning their offsets and dimensions, including the board revision mentioned above? Thank you.
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Forum Post: RE: MSPM0C1104: SysConfig code-gen fails with “Unexpected identifier” due to typo in resourceUsageReport.csv.xdt
Hi Matt, Thanks for reporting this bug. I'll make sure to let our software team know about this. Best Regards, Diego Abad
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Forum Post: RE: TMDSCNCD263P: EEPROM Contents As Delivered From TI
Thank you very much!
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