Part Number: TMS320F280025 Tool/software: Hi, It seems, that the inductance estimation frequency for my ACIM motor is extremly slow and I don't know how to change that. I'm using the MotorControl SDK V5.0.2 with custom hardware. The hardware works fine for PMSM motors so far (identification like in the datasheet on several motors), but for ACIM there seems to be a problem. The overall estimation seems like in the spruhj1i, except the inductance and Rr estimation is extremly slow in my example. From Docu: Measured (Note that there is some noise on the current probe, the actual signal looks pretty good): IdMag: After IdMag found: So the motor works fine after identification, but I'm not sure if the measured inductance is good or not (probably not). The parameters I'm using are: #define USER_MOTOR1_TYPE MOTOR_TYPE_INDUCTION #define USER_MOTOR1_NUM_POLE_PAIRS (1) //Only 1 pole pair #define USER_MOTOR1_Rr_Ohm (NULL) #define USER_MOTOR1_Rs_Ohm (NULL) #define USER_MOTOR1_Ls_d_H (NULL) #define USER_MOTOR1_Ls_q_H (NULL) #define USER_MOTOR1_MAGNETIZING_CURRENT_A (NULL) #define USER_MOTOR1_RATED_FLUX_VpHz (0.8165f*230.0f/50.0f)//(0.8165f*400.0f/50.0f) //STAR: 230VAC, DELTA: 400VAC #define USER_MOTOR1_RES_EST_CURRENT_A (0.5f) #define USER_MOTOR1_IND_EST_CURRENT_A (NULL) #define USER_MOTOR1_MAX_CURRENT_A (2.0f) #define USER_MOTOR1_FLUX_EXC_FREQ_Hz (5.0f) #define USER_MOTOR1_NUM_ENC_SLOTS (NULL) #define USER_MOTOR1_INERTIA_Kgm2 (7.06154e-05f) #define USER_MOTOR1_FREQ_NEARZEROLIMIT_Hz (1.0f) // Hz #define USER_MOTOR1_RATED_VOLTAGE_V (400.0) #define USER_MOTOR1_FREQ_MIN_Hz (1.0) // Hz #define USER_MOTOR1_FREQ_MAX_Hz (400.0) // Hz #define USER_MOTOR1_FREQ_LOW_Hz (5.0) // Hz #define USER_MOTOR1_FREQ_HIGH_Hz (200.0) // Hz #define USER_MOTOR1_VOLT_MIN_V (15.0) // Volt #define USER_MOTOR1_VOLT_MAX_V (650.0) // Volt #define USER_MOTOR1_FORCE_DELTA_A (0.005f) // A #define USER_MOTOR1_ALIGN_DELTA_A (0.001f) // A #define USER_MOTOR1_FLUX_CURRENT_A (1.0f) // A #define USER_MOTOR1_ALIGN_CURRENT_A (USER_MOTOR1_MAX_CURRENT_A) // A #define USER_MOTOR1_STARTUP_CURRENT_A (USER_MOTOR1_MAX_CURRENT_A) // A #define USER_MOTOR1_TORQUE_CURRENT_A (USER_MOTOR1_MAX_CURRENT_A) // A #define USER_MOTOR1_OVER_CURRENT_A (12.0f) // A #define USER_MOTOR1_SPEED_START_Hz (1.0) #define USER_MOTOR1_SPEED_FORCE_Hz (25.0) #define USER_MOTOR1_ACCEL_START_Hzps (10.0) #define USER_MOTOR1_ACCEL_MAX_Hzps (10.0) #define USER_MOTOR1_SPEED_FS_Hz (3.0) // only for encoder, N/A #define USER_MOTOR1_ENC_POS_MAX (USER_MOTOR1_NUM_ENC_SLOTS * 4 - 1) #define USER_MOTOR1_ENC_POS_OFFSET (668) // Only for eSMO, N/A #define USER_MOTOR1_KSLIDE_MAX (1.50f) #define USER_MOTOR1_KSLIDE_MIN (0.15f) #define USER_MOTOR1_PLL_KP_MAX (7.25f) #define USER_MOTOR1_PLL_KP_MIN (1.25f) #define USER_MOTOR1_PLL_KP_SF (5.0f) #define USER_MOTOR1_PLL_KI (2.8125E-06f) // Not used, reserve #define USER_MOTOR1_BEMF_THRESHOLD (0.5f) #define USER_MOTOR1_BEMF_KSLF_FC_SF (2.0f) #define USER_MOTOR1_THETA_OFFSET_SF (1.0f) #define USER_MOTOR1_SPEED_LPF_FC_Hz (200.0f) // for IS-BLDC, N/A #define USER_MOTOR1_RAMP_START_Hz (1.0f) #define USER_MOTOR1_RAMP_END_Hz (30.0f) #define USER_MOTOR1_RAMP_DELAY (1) // for Rs online calibration #define USER_MOTOR1_RSONLINE_WAIT_TIME (60000U) // 5min/300s at 5ms base #define USER_MOTOR1_RSONLINE_WORK_TIME (24000U) //2min/120s at 5ms base So the flux excitation frequency is 5Hz and according to the manual, that should also be used for the inductance estimation, but it seems only to start with that. Any idea, what is going wrong here?
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Forum Post: TMS320F280025: Inductance Estimation ACIM
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Forum Post: TMS320F280039: Phase-shift & frequency changing PWM, missing pulse
Part Number: TMS320F280039 Tool/software: Hi experts, My client is developing Phase-shift & frequency changing function on EPWM1. And meet the issue of missing pulse. (yellow & blue: EPWM1AB; green & purple: EPWM2AB) The EPWM1 have the same frequency with EPWM2. And EPWM1 receive the SYNC event from EPWM2 (when TBCTR = 0) to load the TBPRD from shadow to active. The EPWM1's TBPRD and CMPA are linking to EPWM2. EPWM1 and EPWM2 are up-down counting mode. The AQ for them is CMPA-UP: DOWN and CMPA-DOWN: UP. Their duty is 50%. For EPWM2 there is no TBPHS only frequency changing, for EPWM1 there are both TBTHS and frequency changing. When they changing the the frequency of EPWM from 90k to 70k directly, they will meet the missing pulse events on EPWM1. We refer to this link: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1312604/tms320f28379d-tms320f28379d-phase-shift-pwm-missing-pulse and add the T1 event with AQ. It will reduce the number of missing pulse events but can not stop missing pulse event. Are there any other suggestions for this issue?
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Forum Post: RE: MSP-FET: giving unable to connect error
so if you hit the last picture you show to recovery the MSP-FET, it still not be recovered? - It does not recover, After hitting 'ok' on last picture, it poped-up msg saying "Starting debug session :Loading debug file...Emulator: Initializing update...". It stays in this screen for couple of seconds and went back to the seconds last picture of that document. What do you see in the COM port in PC device manager when you connect the MSP-FET? I do see it gets added under 'Human Interface Device' category. It got added as 'USB input device'. I don't see it under 'Ports (COM & LPT)' category. Under IAR also, I see it as HID_FET, see the screenshot below - Could you install a CCS/ Uniflash to do a program with it? I tried with UniFlash and it gives same error, see below pictures - On the same setup (everything being same including USB cable, ribbon cable, target board, laptop all same), if I just replace the new MSP_FET with my old MSP_FET, it starts working well.
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Forum Post: RE: AM263P4: EPWMs out of sync by 1 clock cycle
Hi Ralph, I took the epwm_synchronization example and did the following examples in sequential order. TBCLK = 200MHz / (8*1) = 25MHz -> Ttbclk = 40ns. Compared EPWM0 -> EPWM1 synchronization. 1. Set EPWM1 to no phase shift. Changes: EPWM1 Phase Shift Value(TBPHS)=0. epwm_synchronization.c::Line146 change ClockP_sleep(5) -> (500) Result: EPWM1 lags EPWM0 by 40ns=1xTBCLK As mentioned up counter with TBCLK count up Result: EPWM1 lag 40ns=1xTBCLK 3. Changing TBCLK to 200MHz. Result: EPWM1 lags 10ns=2xTBCLK This confirms your comments above. That the 2xlag is due to the TBCLK=EPWMCLK. It does not depend on SYNCDIR or clock mode. Thanks for clarifying how the sync works. 2 Questions: Is this an expected chip functionality? I did not see this behavior mentioned in TRM nor the Errata. When using CMPD to generate SYNCOUT for EPWM0 using up/down counter, is the sync pulse generated on the up count or down count? And is this configurable? Thanks PS. I have decided to not use the sync feature at all and simply ensure all TBCTRs are zero'd when TBCLKs are enabled during initialization. Just would be nice to understand how sync works in case we need to sync during operation mode.
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Forum Post: RE: TMS320F28388D: TMS320F28388D: NMI by uncorrectable Error in CM
Hello Yaroslav At the moment I have no more ECC errors if the following line of code was commented out according to a suggestion from TI: //Flash_enableProgramCache(ctrlBase); This deactivates prefetching and the processing of the code becomes somewhat slower. At the same time, I reset DEVICE_FLASH_WATSTATES from 4 back to 2 again. Perhaps this will also help in your case. Regards Simon
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Forum Post: RE: AM263P4: It seems that TI SBL is not started by RBL
The gel script would be part of the CCS package. Please update the same as shown below in the "Advanced tab" of Target configuration in CCS. Upon which, you can get few logs on the CCS console upon connecting to R5 core. Also, I checked with the ROM team and the log mentioned above is not an RBL log Could you please state your exact procedure followed? i.e. stepwise and after which step do you see these logs and where? Regards, Nikhil
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Forum Post: RE: EVM430-FR6047: Calculating V transducer spacing
Reason's for wanting the transducer separation: We'd like to be able to attach the clamped on transducers on the pipe. If grease is used as the ultrasonic couplant between transducer and pipe, the grease gets scraped off as one slides the transducers back and forth while looking for the maximized receive signal. If a rubber strip is used as the couplant, sliding the transducers to optimize signal strength is almost impossible due to the high friction of the rubber material. We'd like to be able to also calculate the time of flight. We'd like to understand why the calculated separation is different from the actual separation. Is the Snell's law calculation not accurate? What else is needed in the model?
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Forum Post: RE: MSPM0G1519: TIMG12 capture using external 32MHz clock and external 1Hz latch signals
Thank you guys for your suggestions. I will have to get a demo board or build a quicky board of just the G1519 to test this because it's a major blocking point before settling on this part for my product development. Two questions: Q1) It's unclear what Helic's comment means. I came across the same 4MHz freq limitation on HFCLK, so I wondered how to select an external 32MHz clock source. However, It sounds like Helic is saying it's not possible, but Bruce is saying it is possible, but not through SYSCONFIG??? Therefore, I don't understand if you two are in agreement or disagreement. Can you clarify? Q2) BTW, it's a 1Hz signal not a 1KHz signal, but not sure that matters with TIMG12 being a 32-bit timer. Q3) SUGGESTION: I like the graphical clock tracing in SYSCONFIG for system clocks, so why not add TIMER clocking into that, also?
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Forum Post: MSPM0G1107: Sharing the same pin for the MISO and GPI function
Part Number: MSPM0G1107 Other Parts Discussed in Thread: ADS114S08B , Tool/software: Hello, I'm considering handling GPI (interrupt) via a pin shared with the MISO on the SPI bus. Actual use case is to read "Data Ready" signal from the ADC (ADS114S08B) via a bus shared with MISO. Regarding MSPM0G1107, are there any options to implement that? Is it the feasible way that changing the peripheral function at runtime, every sampling? Or (possibly), can read logic signals under SPI peripheral configuration with special backup resister or something like that? Thanks.
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Forum Post: RE: TMS320F28P550SJ: Can I use FALSH API to program the OTP?
Hi Shuqing Can you please call below function before program/erase command? This will resolve your issue. Fapi_setupBankSectorEnable(FLASH_WRAPPER_PROGRAM_BASE+FLASH_O_CMDWEPROT_UO, 0x00000000); Refer flash API user guide for more details http://www.ti.com/lit/pdf/sprujc5 Regards, Rajeshwary
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Forum Post: RE: MCU-PLUS-SDK-AM273X: MCU R5F0 core task switching issue
Hi Dhanapal, We are currently waiting for your feedback on the bug fix for system timer overflow issue in MCAL release 09.00.01.01 suggested by Sunil. Best regards, Ming
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Forum Post: RE: AM2434: Removing MUX before Ethernet PHY 1
Hello Jenita Thank you for the query. Would you be able to share the customer board schematics to do a quick check. I amy have to reassign to the software expert after review if the issue observed is not related to hardware. Regards, Sreenivasa
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Forum Post: RE: LAUNCHXL-CC26X2R1: Loading Keys to Key Store Memory
Hello Cetin, This appears to be a continuation of your prior E2E thread . Other than the DMA section of the TRM (Chapter 12.5.3), here are the driverlib and registers for this module. You can try reviewing error values, resetting the DMA, and checking its status. Regards, Ryan
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Forum Post: RE: TMS320F280049: F280049PZS NIPDAU Finish
Yes exactly, it is the same as in the FAQ. I can confirm F280049PZS is roughened lead-frame.
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Forum Post: RE: TIDM-BIDIR-400-12: Inductor L2, AF5667BR
All the information we have on L2 is on the HwdevPkg which I presume you already have. Unfortunately, all the folks which worked on this design are no longer available.
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Forum Post: MSPM0G3507: Configuring DAC12 with custom voltage through the OPA0
Part Number: MSPM0G3507 Tool/software: Howdy! I am attempting to configure my micro for controlling a circuit using the DAC12 connected to the OPA0 using the following settings. The DAC12: The OPA0: I can enable the DAC and OPA0 to operate and disabling their pins drops the voltage to zero, so I know I am not getting supplied voltage from anywhere else, however I am attempting to use the DL_DAC12_output12 ( ) function to manually control the voltage supplied. From what I can gleam from the documentations, supplying a valid value to this function should control the DAC, however I am seeing no change. [ DL_DAC12_output12 (DAC0, config . HeaterV ) where HeaterV is my voltage value 0x4BB ] I am not sure if there is something I am missing about this DAC and OPA0 set up. My pin PA15/19 is floating and set to input, but I'm not sure if that would be the issue. Any help in this would be great!
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Forum Post: RE: MSPM0G1519: TIMG12 capture using external 32MHz clock and external 1Hz latch signals
I think [Helic will correct me?] that Helic was describing using the 32MHz signal to provide one of the system clocks, and routing that to the timer as TIMCLK. I was describing using the 32MHz as a counter-trigger via the (e.g.) C1 pin. Digging a bit further, I think I see the terminology conflict: I think of this (the 32MHz via C1) as a "timer clock" since it drives the counter to tick; the designers consider this a Compare unit feature that (also) causes the counter to tick. Helic (and Sysconfig) are correct that the TIMCLK that runs the rest of the timer unit needs to be one of the system clocks. (This presumably needs to be >=32MHz; BUSCLK seems like a good bet.) The model for this is described in TRM (SLAU846B) Sec 27.2.3.2.1 and illustrated in example timx_timer_mode_compare_edge_count: https://dev.ti.com/tirex/explore/node?node=A__AAR6edrrZqUYodAtIjBtSQ__MSPM0-SDK__a3PaaoK__LATEST In the Example this is done in Driverlib via a (synthesized) mode "DL_TIMER_COMPARE_MODE_EDGE_COUNT" which does the things I described above. I'm not a Sysconfig wizard, but I didn't find a mechanism to Also set the other channel (C0) for Capture. I'm pretty sure the timer unit is capable of it.
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Forum Post: AM2632: UniFlash - Export bootloader and application to single bin file
Part Number: AM2632 Other Parts Discussed in Thread: UNIFLASH , Tool/software: On a pcba that has an AM2632, programmed with a valid SBL image (.tiimage) and Application image (.appimage): is it possible to export the memory to a single .bin file? And then take this single .bin file and program it to another identical board? I use the SBL Image address off-set as my starting point to export the memory. UniFlash gives me an error when I attempt to do this (see attached image). I select SBL Image only when attempting to do this programming. Are there other settings I need to toggle? Thank-you!
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Forum Post: RE: MSPM0G1107: Sharing the same pin for the MISO and GPI function
Generally, you can't use the GPIO to read the state of a pin connected to the SPI, since the IOMUX PFs (Pin Functions) are separate. It is possible to switch the PF on the fly, by changing the PINCM register. In some cases this can produce glitches, but for your MISO pin this may not matter. (I suspect the SPI is idle while you're watching for Data Ready.)
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Forum Post: RE: TMS320F28388D: Accessing peripheral result by both the cores simultaneously
[quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"] 1. Can the both cores access the eCAP result (ECap3Regs.CAP1) at the same time? If they access at same time, what can happen to the result read by both the cores as it can trigger ecap event at same time to both the cores? [/quote] Both cores cannot access the eCAP result at the same time. Which core has access to the peripheral registers will be determined by the CPUSEL register. Please refer to this e2e thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/881378/tms320f28379d-access-to-the-peripherals For example, if CPU1 owns eCAP1, then only CPU1 will be able to read from the eCAP registers. CPU2 will read back 0's. Even though both cores can be triggered by the same interrupt source. [quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"] 2. If I have configured the same interrupt in both the events like ecap3_isr,adc_isr,pwm_isr then do I need to acknowledge in both the cores like below? [/quote] Yes each CPU has their own PIPE. Thus, making sure to get the next interrupt on each core means you'll need to acknowledge both. [quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"]If adc result is read by CPUs, before the result ready or during conversion, will it be previous value or random value?[/quote] The ADC results are duplicated for each CPU, CLA, and DMA so that no arbitration is needed when reading the result registers. If ADC result is read by CPUs before the result is read, it will contain previous value. Best, Ryan Ma
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