Hi WorkerBee, [quote userid="558080" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1473483/mspm0g3507-configuration-for-max-adc-throughput/5709890#5709890"]the time it takes to write a couple of registers to start the next dma should be much less than the time it takes for the ADC's fifo to fill up. [/quote] No exactly. Actually we need to consider the time of entering and exiting from an interrupt and also the DMA configuration time. [quote userid="558080" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1473483/mspm0g3507-configuration-for-max-adc-throughput/5709890#5709890"] is there a dma engine / second processor that does it or is this really code running on the processor?[/quote] Sorry there is only one processor. But I'm not sure what you mean "really code". Best Regards, Pengfei
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Forum Post: RE: MSPM0G3507: Configuration for max ADC throughput
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Forum Post: RE: AM2434: AM243x-LP
Hi Paula, I think we need your help on our site. On this page, https://software-dl.ti.com/processor-industrial-sw/esd/motor_control_sdk/am243x/latest/docs/api_guide_am243x/SDFM_DESIGN.html . EPWM frequency was up to 20 KhZ. Is that the upper limit for customers? Best, Jinlong
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Forum Post: MSPM0G3107: MSPM0 FLASHCTL API
Part Number: MSPM0G3107 Tool/software: I'm having an issue when writing to Flash using the API for flashctl when using the MSPM0 SDK (2.2.0.05, CCS 20.0.2.5). When using the program functions, I'm able to write into memory (after unprotecting, erasing, and unprotecting again); that part seems normal. However, there are times where extra data is being written into memory. Shown below is a breakpoint right before "execute" is called. Registers show the appropriate data I want written into 0x1FC08. However, once it's written, there is an extra two (not seen in CMDDATA0 or CMDDATA1. Just looking for guidance or common scenarios I may be overlooking. Thanks, Rob
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Forum Post: RE: TMS320F28P659SH-Q1: Support from TI regarding the below controllers
all of these products are in the same recent process node and all still considered ACTIVE and latest products. The P65x series is earliest in the life cycle but you can feel confident in choosing any of them.
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Forum Post: RE: AM2434: AM243x-LP
Hi Jinlong, please wait for my colleague to reply here as these are more Motor Control SDK questions (than pure EPWM questions), which I am not familiar with thank you, Paula
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Forum Post: RE: TMS320F280041C: Removal of Flash read protection for sectors 8 to sectors 15 in Bank0 and Bank1
Hi Rana, Are you using DCSM? If not I will reassign this issue to one of our flash/flash API experts. Thank you, Luke
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Forum Post: RE: TMS320F28379D: Synchronizing the rising edge of the EPWM pulse
Nevermind, I saw that there was another place in the code that was overwriting the settings. I commented it out and now it works as expected.
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Forum Post: RE: TMS320F280025C: Issue with CAN_readMessage and CAN_clearMessage Functions in C2000Ware
Hi Joseph, CAN_getInterruptCause is still returning 0x00008000 after replacing CAN_MSG_OBJ_NO_FLAGS by CAN_MSG_OBJ_RX_INT_ENABLE. Is there anything else missing? I have another quick question, if you don’t mind. The F280025's technical reference guide brings some recommendations about the CAN GPIOs configurations, but about the pull-ups it only says "The internal pull-ups can be configured in the GPyPUD register." Is it recommended or not to enable the pull-ups in the CAN GPIOs (considering that a CAN transceiver is used)? Regards, Filipe
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Forum Post: RE: TMDSHSECDOCK: Edge Connector HSEC8-160 wrong orientation and position of pin 1
Hi Eyke, I had a look at a physical TMDSHSECDOCK board and found the same - the pin 1 marking on the part is where 'pin 120' is on the schematic. While there are no plans for a new revision of this board, this will be noted for future HSEC-based docking station EVMs. I apologize for the inconvenience. Regards, Brennan
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Forum Post: RE: TMDSHSECDOCK: Edge Connector HSEC8-160 wrong orientation and position of pin 1
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Forum Post: RE: TMS320F28P650DH: Why freopen function will affect MCAN normally init and MCAN can not run?
Does reconfiguring MCAN after calling the freopen functions resolve your issue? Can you share the latest project files for reference? Best Regards, Zackary Fleenor
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Forum Post: F29H850TU: Where are the EQEP pins on the F29H85x?
Part Number: F29H850TU Tool/software: Hello, I want to route the EQEP on the F29H850TU, and found no indications as where they are. Usually, they are shown up in the Pin Assignation Table. Example from TMS320F28P650: With the F29H85x datasheet, there are no "QEP" mention anywhere in that table. Both devices have Type 2 eQEP, so I do not suspect major difference. Both documentations shows the EQEP signals are coming trough the GPIO MUX: In the GPIO MUX documentation, there seems to be no special mention of the EQEP, implying it is "just another peripheral to select". I have digged in both datasheet and TRM and found nothing. Where are EQEPx_INDEX, EQEPx_A and EQEPx_B pins on the F29H850TU ??? Thanks!
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Forum Post: RE: AM2434: AM243x-LP
Hi Jinlong, with respect to your question if PRU ICSS PWM necessary of SDFM sync with PWM or if we could use EPWM. The answer is that you could use EPWM as well, but I think, when possible, it is better to elaborate on top of a working example from our SDKs thank you, Paula
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Forum Post: RE: MSPM0G3519: MCAL_MSPM0_00.02.04.00
Looking at the library, looks like the vector table and exceptions are located in the startup_iar.c, is this what you are looking for?
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Forum Post: RE: TMS320F28335-Q1: 28335 warning when use library
Hi, Our expert is out of office, please expect a response towards the end of next week. Best Regards, Ben Collier
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Forum Post: RE: MSPM0G3507: Prevent TIMA1 event on re-enable
What's the significance of the number 400? Is this intended to be 1/4th of the period? Would it be affected by new_load_value? It would probably be informative to know which event triggered (TIMA1->GEN_EVENT1.MIS).
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Forum Post: TMS320F28388D: Memory violation at 0x63FF
Part Number: TMS320F28388D Tool/software: Hi, I'm using the following linker file and I have a problem with it, the problem is that I get memory violation at 0x63FF address, I don't touch this memory in my code but I get this violation, I want to know what is the reason ? Because sometimes my code works unpredictable and I guess that could be a reason for that. .cmd file: #ifdef CLA_BLOCK_INCLUDED // Define a size for the CLA scratchpad area that will be used // by the CLA compiler for local symbols and temps // Also force references to the special symbols that mark the // scratchpad are. CLA_SCRATCHPAD_SIZE = 0x100; --undef_sym=__cla_scratchpad_end --undef_sym=__cla_scratchpad_start #endif //CLA_BLOCK_INCLUDED MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 BEGIN_FLASH : origin = 0x080000, length = 0x000002 RAMLS_CLA_DATA : origin = 0x008000, length = 0x002000 RAMLS_CLA_PROG : origin = 0x00A000, length = 0x002000 RAMGS_PROG : origin = 0x014000, length = 0x007000 /* Flash sectors */ FLASHA_N : origin = 0x080002, length = 0x03FFFE /* on-chip Flash */ RESET : origin = 0x3FFFC0, length = 0x000002 PAGE 1 : BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */ RAMM0M1 : origin = 0x0001B0, length = 0x000650 RAMD0D1 : origin = 0x00C000, length = 0x001000 RAMGS_DATA : origin = 0x010000, length = 0x004000 CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 CPUTOCMRAM : origin = 0x039000, length = 0x000800 CMTOCPURAM : origin = 0x038000, length = 0x000800 CANA_MSG_RAM : origin = 0x049000, length = 0x000800 CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 #ifdef EMIF1_CS0_INCLUDED EMIF1_CS0_MEMORY : origin = 0x80000000, length = 0x10000000 #endif //EMIF1_CS0_INCLUDED #ifdef EMIF1_CS2_INCLUDED EMIF1_CS2_MEMORY : origin = 0x00100000, length = 0x00200000 #endif //EMIF1_CS2_INCLUDED #ifdef EMIF1_CS3_INCLUDED EMIF1_CS3_MEMORY : origin = 0x00300000, length = 0x00080000 #endif //EMIF1_CS3_INCLUDED #ifdef EMIF1_CS4_INCLUDED EMIF1_CS4_MEMORY : origin = 0x00380000, length = 0x00060000 #endif //EMIF1_CS4_INCLUDED #ifdef EMIF2_CS0_INCLUDED EMIF2_CS0_MEMORY : origin = 0x90000000, length = 0x10000000 #endif //EMIF2_CS0_INCLUDED #ifdef EMIF2_CS2_INCLUDED EMIF2_CS2_MEMORY : origin = 0x00002000, length = 0x00001000 #endif //EMIF2_CS2_INCLUDED } SECTIONS { /* Allocate program areas: */ codestart : > BEGIN_FLASH, PAGE = 0, ALIGN(8) .text : > FLASHA_N, PAGE = 0, ALIGN(8) .cinit : > FLASHA_N, PAGE = 0, ALIGN(8) .switch : > FLASHA_N, PAGE = 0, ALIGN(8) #if defined(__TI_EABI__) .init_array : > FLASHA_N, PAGE = 0, ALIGN(8) /* Initalized sections go in Flash */ .const : > FLASHA_N, PAGE = 0, ALIGN(8) .data : > RAMGS_DATA, PAGE = 1 .TI.ramfunc : {} LOAD = FLASHA_N, RUN = RAMGS_PROG, LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd), RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd), PAGE = 0, ALIGN(8) ramfuncs : LOAD = FLASHA_N, RUN = RAMGS_PROG, LOAD_START(MW_RamfuncsLoadStart), LOAD_SIZE(MW_RamfuncsLoadSize), LOAD_END(MW_RamfuncsLoadEnd), RUN_START(MW_RamfuncsRunStart), RUN_SIZE(MW_RamfuncsRunSize), RUN_END(MW_RamfuncsRunEnd), PAGE = 0, ALIGN(8) #else .pinit : > FLASHA_N, PAGE = 0, ALIGN(8) /* Initalized sections go in Flash */ .econst : > FLASHA_N, PAGE = 0, ALIGN(8) .TI.ramfunc : {} LOAD = FLASHA_N, RUN = RAMGS_PROG, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(8) ramfuncs : LOAD = FLASHA_N, RUN = RAMGS_PROG, LOAD_START(_MW_RamfuncsLoadStart), LOAD_SIZE(_MW_RamfuncsLoadSize), LOAD_END(_MW_RamfuncsLoadEnd), RUN_START(_MW_RamfuncsRunStart), RUN_SIZE(_MW_RamfuncsRunSize), RUN_END(_MW_RamfuncsRunEnd), PAGE = 0, ALIGN(8) #endif // defined(__TI_EABI__) #if defined(__TI_EABI__) .bss : >> RAMGS_DATA , PAGE = 1 #else .ebss : >> RAMGS_DATA , PAGE = 1 #endif // defined(__TI_EABI__) /* Allocate IQmath areas: */ IQmath : > FLASHA_N, PAGE = 0, ALIGN(8) /* Math Code */ IQmathTables : > FLASHA_N, PAGE = 0, ALIGN(8) #if defined(__TI_EABI__) .sysmem : > RAMD0D1, PAGE = 1 #else .esysmem : > RAMD0D1, PAGE = 1 .cio : > RAMGS_DATA, PAGE = 1 #endif // defined(__TI_EABI__) .stack : > RAMM0M1, PAGE = 1 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, PAGE = 1, ALIGN(4), TYPE = NOINIT MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, PAGE = 1, ALIGN(4), TYPE = NOINIT MSGRAM_CPU_TO_CM : > CPUTOCMRAM, PAGE = 1, ALIGN(4), TYPE = NOINIT MSGRAM_CM_TO_CPU : > CMTOCPURAM, PAGE = 1, ALIGN(4), TYPE = NOINIT #if defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED) .farbss : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY, PAGE = 1 .farconst : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY, PAGE = 1 #elif !defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED) .farbss : > EMIF2_CS0_MEMORY, PAGE = 1 .farconst : > EMIF2_CS0_MEMORY, PAGE = 1 #elif defined(EMIF1_CS0_INCLUDED) && !defined(EMIF2_CS0_INCLUDED) .farbss : > EMIF1_CS0_MEMORY, PAGE = 1 .farconst : > EMIF1_CS0_MEMORY, PAGE = 1 #else //No EMIF memory sections #endif //defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED) #ifdef EMIF1_CS0_INCLUDED Em1Cs0 : > EMIF1_CS0_MEMORY, PAGE = 1 #endif //EMIF1_CS0_INCLUDED #ifdef EMIF2_CS0_INCLUDED Em2Cs0 : > EMIF2_CS0_MEMORY, PAGE = 1 #endif //EMIF2_CS0_INCLUDED #ifdef EMIF1_CS2_INCLUDED Em1Cs2 : > EMIF1_CS2_MEMORY, PAGE = 1 #endif //EMIF1_CS2_INCLUDED #ifdef EMIF1_CS3_INCLUDED Em1Cs3 : > EMIF1_CS3_MEMORY, PAGE = 1 #endif //EMIF1_CS3_INCLUDED #ifdef EMIF1_CS4_INCLUDED Em1Cs4 : > EMIF1_CS4_MEMORY, PAGE = 1 #endif //EMIF1_CS4_INCLUDED #ifdef MW_EMIF2_CS2_INCLUDED Em2Cs2 : > EMIF2_CS2_MEMORY, PAGE = 1 #endif //MW_EMIF2_CS2_INCLUDED } /* //=========================================================================== // End of file. //=========================================================================== */
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Forum Post: RE: MSPM0C1103: wake from SHUTDOWN
So it seems lilke TI really needs to get the documentation cleaned up for the C series. If this forum post is correct, then the C series does not support IO wakeup from STANDBY mode: e2e.ti.com/.../mspm0g3107-mspm0c1104-shutdown-wake-with-io-issue
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Forum Post: AM2612: Motor control SDK docu
Part Number: AM2612 Tool/software: Hi, where can I find the Motor Control SDK and docu like we have for AM243x: https://dev.ti.com/tirex/explore/node?node=A__AD2nw6Uu4txAz2eqZdShBg__MOTOR-CONTROL-SDK-AM243X__2dDFdJs__LATEST Can I use the same motor position sensing ICSS firmware like for AM243x? Regards, Holger
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Forum Post: RE: TMS320F28021: How to read data and write on other mcu
Hi Zubair, In CCS you can perform a memory dump of the Flash memory. In the CCS "View" option, select from the dropdown the "Memory" tab. There should be an arrow next to the "Format" dialog box to export the memory, where an "Export Data" dialog box will be shown. You should then provide a file name, file format and Address for starting memory range w/ Length in words. Once ready, click ok to save your data to your generated file. You can then load this data through CCS/Uniflash for the next device you have. Thanks and regards, Charles
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