Part Number: TMDSCNCD28379D Tool/software: Hi, I am using TMDSCNCD28379D and measured all PWM signals. PWM1,2,3,4 are working as expected but PWM5, 6 have no outputs. Do I need to do anything else for this two PWMs? Thanks, Hongmei Wan
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Forum Post: TMDSCNCD28379D: EPWM5 and EPWM6 not working
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Forum Post: RE: AM2634: AM263X & F28P65X : CAN communication issue
Hi Fleenor, As previously mentioned, MCAN communication within the same board, using loopback mode, is functioning correctly. Additionally, communication between two identical boards is also working as expected. However, when attempting to establish MCAN communication between an AM263X_CC board and an F28P65X board, the communication fails. We are encountering the MCAN_INTR_SRC_PROTOCOL_ERR_DATA interrupt, and transmission is failing due to the condition: can_bus->tx_done! = true not being met. Furthermore, even after setting the S4 (CAN ROUTE) switch to 0, the issue persists. We need guidance on how to proceed further in troubleshooting and resolving this issue. Could you provide insights into potential causes and debugging steps?
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Forum Post: RE: AM2432: EtherCAT Slave connecting to KEYENCE KV7500 not successful
Hi Rasty, [quote userid="359686" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1485196/am2432-ethercat-slave-connecting-to-keyence-kv7500-not-successful/5711838#5711838"]5. Most important we use PRG0, not PRG1 PRG0 _PRU0_GP I 8 and PRG0 _PRU1_GPI8 [/quote] Thank you for this information. Looks like there's a misconfiguration in our application for EtherCAT on ICSSG0 Demo when MDIO Manual Mode is enabled. Can you confirm if it is enabled in your application? If this is enabled, you will have to update the following lines of code in tiesc_mdioManualModeSetup() present in tiescsoc.c file: /* Pass value to R10 of TX_PRU core for MDIO FW WA Configuration */ CSL_REG32_WR(CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_10, MDIO_MANUAL_MODE_FW_CONFIG_VALUE); /* Pass value to R12 of TX_PRU core for emulated MDIO Base Address */ CSL_REG32_WR(CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_12, MDIO_MANUAL_MODE_BASE_ADDRESS); should be changed to /* Pass value to R10 of TX_PRU core for MDIO FW WA Configuration */ CSL_REG32_WR(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_10, MDIO_MANUAL_MODE_FW_CONFIG_VALUE); /* Pass value to R12 of TX_PRU core for emulated MDIO Base Address */ CSL_REG32_WR(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_12, MDIO_MANUAL_MODE_BASE_ADDRESS);
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Forum Post: TMS320F2800157: CAN Communication between f2800157 and APSoC zc702 board
Part Number: TMS320F2800157 Tool/software: Hi i need to make communication between f2800157 microcontroller and zynq zc702 APSoC through CAN. connection can_h (ti) to can_h(apsoc) can_l (ti) to can_l(apsoc) gnd to gnd Whether this connection is correct? i just need to verify the CAN is working is working or not between this. so in ti i will run the example loopback.c and in apsoc i will use canopen to send, or see the incoming data's through can
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Forum Post: TMS320F28335-Q1: 28335 warning when use library
Part Number: TMS320F28335-Q1 Tool/software: Hi experts, Good day! I am asking for customer. My customer is facing following warnings when using library. Could you give us some suggestions to eliminate these warnings? Thanks! Best Regards Kita
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Forum Post: RE: TMS320F2800157: CAN Communication between f2800157 and APSoC zc702 board
Ryan Ma
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Forum Post: RE: MSPM0L1106: Question on GPIO settings :
On the Launchpad there is a resistor connected to PA2 for Rosc. I don't know why they don't put a jumper:
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Forum Post: TMS320F28377D: jitter on PWM when using HR mode
Part Number: TMS320F28377D Other Parts Discussed in Thread: C2000WARE Tool/software: Hello, Currently, I have an issue with the use of HRPWMs on the comparators of a TMS320F28377D. When using them in UP and DOWN counting mode with dead bands, and PWM2/3/4/5/6/7/8 are linked to PWM1. Indeed, despite using shadow mode, the CMPA and CMPAHR registers do not seem to be loaded at the same time, which causes jitter. To verify my current configuration and check my suspicions, I tested the example code "hrpwm_ex9_dutyhr_updown_deadband_sfo" (from C2000Ware_5_04_00_00) by slightly modifying it to highlight the issue. Specifically, I modify the register value to primarily increment the CMPAHR register and make a jump of +1 on CMPA. Here is the result in the picture: - In 1, you can clearly see my variation with my +1 increments, - In 2 and 3, the jitter. This is really not acceptable in my product; is there a way to work around this problem? Thank you in advance. Best regards, Martial ARNAUD PS: here the test code that allows reproducing the issue e2e.ti.com/.../hrpwm_5F00_ex9_5F00_dutyhr_5F00_updown_5F00_deadband_5F00_sfo_5F00_jitter.c
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Forum Post: RE: MSP430FR6043: EIC Interrupt missing edges
You mentioned that your signal is PWM (125Hz/4ms). Is it close to 50% duty, or at least not close to 0% or 100%? That would be the prime hazard: If two edges appeared very close together. How do you tell that edges are being missed? (Scope? Counter? Debugger?)
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Forum Post: RE: AM2634: ENET CPSW for multicore
Hi Shaunak What Ethernet applications do you run on two R5F cores? → I will be running two different Ethernet server applications, each assigned to a separate R5F core. These servers will operate independently, ensuring that network communication for each application is handled separately. Each core will manage its respective Ethernet port, allowing for efficient and isolated processing of network traffic. What is the limitation of using just one R5F core to handle all requirements? → A single R5F core managing both Ethernet server applications could lead to resource contention, increased processing load, and potential scheduling conflicts. By assigning each core to a dedicated Ethernet port, the system ensures isolated and efficient processing, prevents interference between servers, and enhances overall performance and reliability. What are your throughput and latency requirements? (for both cores) → The system is designed to achieve a throughput of 1 Gbps while maintaining a latency of 50–200 µs per packet, ensuring efficient and high-speed Ethernet communication.
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Forum Post: RE: MSPM0G3507: CAN RX with DMA
Hi and thanks! [quote userid="452230" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1484192/mspm0g3507-can-rx-with-dma/5704929#5704929"]I don't see the number of transfers set, so make sure you have the correct number with regards to how much data you're transferring per transfer.[/quote] What do you mean by "number of transfers"? _____________________________________________________________________________________________ [quote userid="452230" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1484192/mspm0g3507-can-rx-with-dma/5704929#5704929"] I'm looking into what address space you need to view to see the RX CAN buffer.[/quote] Thanks, I quickly found my CAN RX FIFO0 in address 0x2010.0000. I can see every CAN Msg that I receive in the memory starting from this address. I am wondering why every CAN frame takes 42 * 32Bit in this memory. According to this Figure 21-21 I would have expected a size of 4 * 32Bit for one CAN Frame with 8 Data Bytes. Please clarify ;) _____________________________________________________________________________________________ And just another short question: is there any possibility to adjust the view so that I see each new message in a new line, i.e. a line break after each CAN frame in this memory view? _____________________________________________________________________________________________ I also see the &gRxDataframe[0], the destination for the DMA-Transfer, in the memory view. But the memory values stay "0" even though I receive a CAN message, see it in the FIFO memory view and - debugged via breakpoint - that the "DL_DMA_startTransfer(DMA, DMA_CH0_CANRX_CHAN_ID);" got executed. Any idea what I am missing? What might still go wrong? Thanks a lot in advance! Best regards! Matze
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Forum Post: LP-MSPM0G3507: JTAG Communcation ERROR
Part Number: LP-MSPM0G3507 Other Parts Discussed in Thread: MSPM0G3507 Tool/software: Hi there, When I debug my Code on the launchpad MSPM0G3507 using CCS 20.1.0 i frequently get the following error message: JTAG Communication Error: (Error -1001 @ 0x0) Requested operation is not supported on this device. (Emulation package 20.1.0.3372) Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging I set the device to factory settings and did not set any breakpoints. Any ideas to improve? Best regards
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Forum Post: RE: MSPM0L2227: Interrupt pin
I am not sure what you mean by "switch", but make sure it has the proper de-bouncing.
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Forum Post: RE: AM2432: EtherCAT Slave connecting to KEYENCE KV7500 not successful
Hi I don't see where MDIO_MANUAL_MODE_ENABLED. We globally replaced CSL_PRU_ICSSG1 with CSL_PRU_ICSSG0 in all the places, assuming that no other adaptation required if we move Ethercat from ICSSG1 to ICSSG1, plus adjustment of PRU events, plus sysconfig. It worked 99% except link indication. Thanks rasty #ifdef MDIO_MANUAL_MODE_ENABLED void tiesc_mdioManualModeSetup() { int32_t status; /* ----------------------------------------------------------------- */ /* Load the MDIO firmware binary on PRU Core; */ /* ----------------------------------------------------------------- */ /* Reset Core */ status = PRUICSS_resetCore(pruIcss1Handle, PRUICSS_PRUx); DebugP_assert(SystemP_SUCCESS == status); /* Disabe Core */ status = PRUICSS_disableCore(pruIcss1Handle, PRUICSS_PRUx); DebugP_assert(SystemP_SUCCESS == status); /* Load firmware. Set buffer = write to PRU memory */ status = PRUICSS_writeMemory(pruIcss1Handle, PRUICSS_IRAM_TX_PRU(0), 0, (uint32_t *) PRUFirmware, sizeof(PRUFirmware)); DebugP_assert(status != 0); /* Pass value to R10 of TX_PRU core for MDIO FW WA Configuration */ CSL_REG32_WR(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_10, MDIO_MANUAL_MODE_FW_CONFIG_VALUE); /* Pass value to R12 of TX_PRU core for emulated MDIO Base Address */ CSL_REG32_WR(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX0_IRAM_DEBUG_REGS_BASE + PRU_REG_12, MDIO_MANUAL_MODE_BASE_ADDRESS); /* Run firmware */ status = PRUICSS_enableCore(pruIcss1Handle, PRUICSS_PRUx); DebugP_assert(SystemP_SUCCESS == status); } #endif
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Forum Post: RE: MSPM0G3507: CAN RX - messages are not received reliably
Hi, in the mean time I found out that my problems in CAN reception were caused by the 80 MHz that I set for CAN-frequency. After I changed my CAN-frequency to 40 MHz my problems in CAN reception were gone! But I don't know, why the 80 MHz didn't work errorless. [quote userid="278451" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1485613/mspm0g3507-can-rx---messages-are-not-received-reliably/5708724#5708724"]I agree with you that it is very uncommon that the very first message not to arrive and then the "Message RAM Access Failure bit" is set for the second message that arrives. [/quote] Concerning this issue I also found out why and need to clarify: The "Message RAM Access Failure bit" was set when the can rx interrupt of the second Msg came in because the MRAF-Interrupt was not enabled but the bit nonetheless got set when the message reception crashed. But I only saw that the MRAF bit is set when the new-message-interrupt of the second message was triggered. Since I have also activated the MRAF interrupt, an interrupt containing the MRAF flag is also triggered when the first message crashes. Each interrupt flag is now correctly assigned to the corresponding CAN message received.
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Forum Post: RE: AM2612: API OSPI _readCmd issue
Hi Rijohn, Thanks for your reply. I understood. Please enjoy your holiday first!
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Forum Post: RE: MSP430FR6043: EIC Interrupt missing edges
If it were me, I would use two pins. One configured for the rising and the other for the falling edge. Then read P6IV in the ISR to find out which one caused the interrupt. No need to read P6IN or change P6IES.
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Forum Post: RE: MSPM0G3519: MCAL_MSPM0_00.02.04.00
Let me check, I think it should all be in there, but I will double check to make sure.
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Forum Post: RE: LP-XDS110ET: Can LP-XDS110ET support debug C2000 devices?
Hi Fengyu, This can work fine, but sometimes customers experience signal integrity issues due to the long jumper wires. If you encounter issues, please try to minimize wire length or reduce your JTAG TCK speed. Best, Matt
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Forum Post: RE: TMS320F2800157: Why are the reserved bits of EXTROSCCSR1 used in driverlib codes?
Hi Wayne, Anything that is bounded by the if condition from line 266 to 287 should be removed as those codes all pertain to EXTR oscillator mode. Regatrds, Joseph
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