Sorry that wasn't clear, simply we want pins 6 and 7 to match pins 12 and 15 in functionality. We previously had one multiplexer on our custom PCB, and we recently added a second. Pins 12 and 15 are on the original component, 6 and 7 will do the same functionality but on the newly added mux
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Forum Post: RE: SIMPLELINK-CC2640R2-SDK: How to edit the Simplelink SDK as to change the functionality of pins
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Forum Post: RE: AM2634-Q1: AM263xB/C SDK
Hi Holger, The same sdk works for different OPN numbers of AM2634. So no, you do not need separate sdk.
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Forum Post: RE: AM2634-Q1: AM263xB/C SDK
May I know why this question is coming
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Forum Post: RE: TMS320F28388D: InstaSPIN-FOC/FAST Estimator Usage on F2838
So what is the F2838 device ID register PARTIDL InstaSPIN-FOC (0x1) referring to ?
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Forum Post: TMS570LS1224: Using Watchdog as part of Hercules Bootloader Example
Part Number: TMS570LS1224 Tool/software: I'm trying to add a watchdog interrupt as part of the example bootloader project: 6.1. Project 0 — Hercules Safety MCUs Documentation . However, it seems to keep resetting my project whenever a function from the Fapi library is used, like Fapi_initializeFlashBanks().
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Forum Post: RE: TMS570LS1224: Using Watchdog as part of Hercules Bootloader Example
To add, I am adding dwdReset() throughout the project to make sure the watchdog is reset more than enough, including before Fapi_initiializeFlashBanks().
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Forum Post: RE: TIDM-02000: Query Regarding Slope Compensation in 3kW DC/DC Converter Design (Based on TIDM-02000)
[quote userid="13605" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1465785/tidm-02000-query-regarding-slope-compensation-in-3kw-dc-dc-converter-design-based-on-tidm-02000/5668068#5668068"]I discussed with a colleague. It is conceivable that you are hitting the corner condition where COMPHSTS is coming after the EPWMSYNCPER signal as shown in the diagram below. [/quote] Are the CMPSS (input / outputs) Asynchronous events to ePWM Synchronous PRD clock, yes. Seemingly the HV_FB fault trigger OVC trip point is a hardwired RC time constant? One might imagine no CBC trigger pules get to ePWM_DAC when the AC side current peaks remain below a preset RMS peak? HV_FB signal could be of varying width, edge events only occur relative to actual OVC faults. So, the CMPSS output pulse width trips CBC the MDAC only when the edge event (offset) is of certain width relative ePWM pulse width. Otherwise MDAC ignores CMPSS pulses with shorter edge events due to blanking in the ePWM duty cycle pulse width. x49c MCU class /* Set CMPSS2 Blanking of LATCHCLR0-ePWM1 */ CMPSS_configBlanking(CMPSS2_BASE, 1); /* Set CMPSS4 Blanking of LATCHCLR1-ePWM2 */ CMPSS_configBlanking(CMPSS4_BASE, 2); /* Enable CMPSSx Blanking of LATCHCLR */ CMPSS_enableBlanking(obj->cmpssHandle[cnt]); // ePWM Fault Edge Balnking: /* Set the DC-1A/1B BLANKWDW to sync PWM periods * TRM: 18.1.4.2 PG.1878 Figures 18-54/55 */ EPWM_setDigitalCompareBlankingEvent(obj->pwmHandle[cnt], EPWM_DC_WINDOW_START_TBCTR_ZERO); //EPWM_DC_WINDOW_START_TBCTR_PERIOD /* Set DCx offset between window start pulse and blanking * window in number TBCLK's(10ns), offset=10µs */ EPWM_setDigitalCompareWindowOffset(obj->pwmHandle[cnt], 1000); /* Set DCx filter blanking window width TBCLK(10ns), width=5µs */ EPWM_setDigitalCompareWindowLength(obj->pwmHandle[cnt], 500); /* Enable the DCx Blanking window */ EPWM_enableDigitalCompareBlankingWindow(obj->pwmHandle[cnt]); /* Sset the Edge filter mode for Rise/Fall */ EPWM_setDigitalCompareEdgeFilterMode(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_MODE_RISING); /* Set DC filter 1 edge count required to trigger DC events */ EPWM_setDigitalCompareEdgeFilterEdgeCount(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_EDGECNT_1); /* Enable the DC edge filter */ EPWM_enableDigitalCompareEdgeFilter(obj->pwmHandle[cnt]); Point to consider, AC line voltage EURO 200V 50Hz versus USA 118V 60Hz. Seemingly the OVC filter circuit (HV_FB) for EURO DC-DC might have few differences over US filter design?
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Forum Post: RE: AM2632: ECAP usage
Hi zx, Thank you for sharing the project, I have gone through it, xbar routing and interrupt configurations seem correct, and you have already confirmed input signal presence. I have also confirmed that this issue is reported on multiple boards. Just confirming, this project is the testcase where you are using PRU_PRU0_GPIO0? I'll try some configurations tomorrow and get back to you with a clearer answer. Thank you so much for your patience! If there are any other updates you have, or discoveries during your troubleshoot please let me know. Thanks and regards Akshit
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Forum Post: RE: MSPM0G3507: Add a password-protected JTAG locking mechanism to MSPM0G3507
Hi Dylan, I managed to unlock my MSPM0 with the password from Code Composer Studio. I s-it only possible to unlock the MSP with Code Composer Studio and MSPM0_Factory_Reset_Tool ? Thank you
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Forum Post: RE: TMS320F28P650DH: How does SysConfig ClockTree view affect the EPWMCLKDIV setting
Hi Prarthan, I am working with rperezti and he is helping us out with this same issue as well. In my device.c code, I'm not seeing those clock tree configurations lines of code. Does the clock tree tool need another compiler or something of the sort installed in order to generate the code in device.c?
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Forum Post: RE: AM2634-Q1: AM263xB/C SDK
Hi Nilabh, customer had a problem on their HW that the SBL no longer worked. It includes XAM2634B. Regards, Holger
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Forum Post: RE: TMS320F2800157: 48V Encoder motor sometimes running in uncontrolled maximum speed - Alignment issues
[quote userid="578806" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1424244/tms320f2800157-48v-encoder-motor-sometimes-running-in-uncontrolled-maximum-speed---alignment-issues/5670230#5670230"]Can I able to use this logic in DRV8353 EVM because as I know, in universal motor code, this logic is not there.[/quote] Perhaps add SPI regen control code in the brake function, change DRV8320RS to DRV8353xx in the above SPI calls. Change flying flag test to the brake flag control. Be sure to check Nominal bus voltage inside the UMCSDK updated brake & regen function. If you can imagine such design, it can become a reality (:-) [quote userid="578806" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1424244/tms320f2800157-48v-encoder-motor-sometimes-running-in-uncontrolled-maximum-speed---alignment-issues/5670230#5670230"]Any DRV IC related variables we need to take care for this issue.[/quote] The gate driver is designed to handle this directly but you can ask the forum in another post about any other registers.
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Forum Post: MSP430FR2633: Captouch library I2C register mode buffer sizing
Part Number: MSP430FR2633 Tool/software: Hello, I have a customer who's looking at using the captivate library in I2C register mode, and he had some questions on supported message formats and supported lengths that we were hoping to clear up? In register mode, does the library support the general purpose packet? It doesn't seem to get referenced in this operation mode. Another question on the general purpose packet is that the captivate technology guide suggests that the max length of the general purpose packet is 58 bytes, but in code I see the I2C transmit buffer is capped at 32 bytes, and then elsewhere I see the tx ping pong buffers get set up at 48 bytes. What's the max length of the general purpose packet? The last question was in register mode, for a cycle packet does the firmware support sending all 12 channels of data in one cycle packet? Again since the I2C tx buffer is 32 bytes which would not support 12 * 4 bytes of data + the packet header. Munan
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Forum Post: RE: TMS320F28P650DH: How does SysConfig ClockTree view affect the EPWMCLKDIV setting
Hi Mike, Please check the whole Device_init() function, from your screenshot I can see the whole function Also enable the device support in sysconfig
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Forum Post: RE: MSP430FR2476: Low Power mode
If I switch the TA0 output to TA0.2 (P1.2) I get ~6uA with CCR2=30 [EnergyTrace]. Evidently the temperature sensor output (circuit) on P1.1 sets up a bus conflict even if the sensor is unpowered (J9 jumper removed). I hadn't noticed that before. [Edit: Fixed typo.]
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Forum Post: RE: TMS320F2800157: 48V Encoder motor sometimes running in uncontrolled maximum speed - Alignment issues
[quote userid="578806" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1424244/tms320f2800157-48v-encoder-motor-sometimes-running-in-uncontrolled-maximum-speed---alignment-issues/5670230#5670230"]As I mentioned above, in my logic, I am able to generate pwm with fixed duty cycle but across HiGH-SIDE MOSFETs I am getting ramp pulses but across micro controller pin side I am not getting this pulses.[/quote] Doesn't matter when DRV8353 gate drives are in high impedance, gates don't do anything NFET freewheel body diodes handle AC to DC rectification. You could also set both ePWM action qualifiers high impedance in the same function call. Change action qualifiers when the bool brake flag changes state, comment (//) ePWM period change is not required for regen braking.
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Forum Post: RE: AM2634-Q1: AM263xB/C SDK
Holger, sample starting with X is an APL sample. Where does it fail, more info would help us debug this further.
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Forum Post: LP-AM243: Logging from the same UART interface for all cores
Part Number: LP-AM243 Other Parts Discussed in Thread: SYSCONFIG Tool/software: Hi; I want to assign the interface for UART logging of all cores to USART0. However, when I make this assignment from the sysconfig DebugP tab from multiple cores, I get a conflict error as expected. In short, I want to use USART0 for logging function of all cores. How can I provide this functionality? Maybe there is a way to do this using the DebugP_shmLogRead() method? Is it possible to write the logging data of all cores to shared memory with one method and then send it via USART0 with a single core using the DebugP_shmLogRead method? Regards Kadir
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Forum Post: RE: MSP430F5527: Modifying MPS430 Keyboard Project: Changing Consumer Control Report Usage ID from 8-bit to 16-bit
I have found the solution. Thank you both for replying, your input helped my accidentally stumble upon the solution. In descriptors.c there is an array of interface sizes which does not pull the #defines. This array is used by the host. uint16_t const report_desc_size[HID_NUM_INTERFACES] = { 63, 36, 49, 25 }; This array should be updated to use the #defines from descriptors.h //*********************************************************************************************** // DESCRIPTOR CONSTANTS //*********************************************************************************************** #define SIZEOF_DEVICE_DESCRIPTOR 0x12 #define MAX_STRING_DESCRIPTOR_INDEX 8 #define report_desc_size_HID0 63 #define report_desc_size_HID1 36 #define report_desc_size_HID2 51 #define report_desc_size_HID3 25 //#define SIZEOF_REPORT_DESCRIPTOR 36 //#define USBHID_REPORT_LENGTH 64 // length of whole HID report (including Report ID) #define CONFIG_STRING_INDEX 4 #define INTF_STRING_INDEX 5 #define USB_CONFIG_VALUE 0x01 //In descriptors.c uint16_t const report_desc_size[HID_NUM_INTERFACES] = { report_desc_size_HID0, report_desc_size_HID1, report_desc_size_HID2, report_desc_size_HID3 };
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Forum Post: TMS320F28P650DK: Do CPU2 & CLA self test at the same test
Part Number: TMS320F28P650DK Tool/software: Hi experts, In the F28P65x_CLA_STL_API_User's_Guide.pdf In the F28P65x_C28x_STL_API_User's_Guide.pdf Both of CPU2 and CLA test need to use 0x8000. How to do the CPU2 & CLA test at the same time? Thanks, Leo
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