Ilmars is right. Master and slave aren't synchronized. There are two main reasons for this:
First: you don't use the same phase and polarity settings for both. Note that the MSP clock polarity is inverted to the Motorola notation.
Second: the slave recognizes the master's port initialization as clock signal. So the slave receives one bit more than (intentionally) sent, and all following bits shift by one.
You need to keep the slave in reset until the master selects the slave. The STE pin does NOT synchronize the shift register. It only controls the output and input gates (shutting the slave data output and the clock input off)
You shouldn't release the slave from reset while the chip select/STE is active (which means that eitehr the master isn't initialized or a transmission ahs alredy begun and you missted its start). And once the chip is delesected, reset the slave USCI.