Hi Thao, The TXFFIL/RXFFIL is the FIFO level I mentioned before. Having a larger FIFO level won't necessarily increase the rate of data transfer (if you are talking about DMA transfer rate) but rather will allow you to temporarily store more data at a time to be transmitted/received via SPI. Due to this, using a higher FIFO level will allow you to use an increased SPI baud rate without losing data (without overwriting the FIFO as quickly). A DMA interrupt can be configured to trigger either at the start of a transfer or at the end of a transfer. In this example case from the TRM, if the end of transfer DMA interrupt was configured, then yes, the DMATX interrupt would trigger after 200 words have been transferred to the TX buffer (and then transmitted) and the DMARX interrupt would trigger after 200 words have been received and transferred. Best Regards, Delaney
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