Hi Ozino, thank you for the answer. Since there is no example for the IPC communication from CM to CPU1, I checked the IPC Module — F2838x CM API Guide document where it is stated that " With very few exceptions, the same IPC APIs are used by all the 3 processors." Therefore, in the example ipc_ex2_msgqueueand I: 1. Cut __interrupt void IPC_ISR1() from CM code and pasted it into CPU1 code by correcting IPC_CM_L_CPU1_R -> IPC_CPU1_L_CM_R 2. Cut the communication code in the main() from CPU1 and pasted it into CM code, also correcting IPC_CPU1_L_CM_R -> IPC_CM_L_CPU1_R 2.1 Sending and reading message is done twice (double message) by simple copy-pasting correponding code from the example 2.2 I put a short delay between messages just to be sure that there is no sync problem 3. #pragma DATA_SECTION(readData, "MSGRAM_CM_TO_CPU1") is moved to CM code with corresponding correction. 4. I checked the example for the communication between CPU1 and CPU2 and added "Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);" which was not available in CM code This is pretty much all and I pasted the updated code in my first message. This updated CM->CPU1 communication works correctly but only for the first message. The second message is stuck in CM code, interrupt on CPU1 is triggered only by the first message. I tried also similar "double message communication" from CPU1 to CM and this works without problem, triggering interrupt every time the message queued. Since I didn't add a single line of code of my own but just adapting the original code, I call it reversed communication. Btw, the similar double message problem from CM to CPU1 appears also in the ipc_ex1_basic example. I hope, my explanantion is clear enough. Regards, Stanislav
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