I think this is a recognised (but not well documented) phenomenon. I found the following in C:\ti\mcu_plus_sdk_am263px_10_01_00_34\examples\drivers\epwm\epwm_synchronization\epwm_synchronization.c /* When the Sync Pulse arrives, the rising edge is detected and the EPWM holds the state of the Sync singal present. The phase shift value is loaded to the TB Counter of EPWM on the next valid TBCLK. This may cause a TBCLK delay on the "Synced" PWM with the "Syncing" PWM. Hence the 1 count difference in the validation */ I could not find a similar note in the TRM but that is not to say it isn't there. Like I say, not well documented.
↧