[quote userid="637270" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1458312/tms320f28p550sj-configurable-logic-block-clb---how-do-i-get-started/5641957#5641957"] but the communication rate doubled the expected value (5Mbps, sysclk=150M, TFORMAT_CLB_CLK=75M, TFORMAT_BUS_CLK=2.5M). Therefore, I changed TFORMAT_CLB_CLK to 150M. 1. Should TFORMAT_CLB_CLK actually be sysclk/2? [/quote] On the P65x, the CLB can be clocked either from the ePWM clock or from the AUXPLL. If you have configured the device for SYSCLK = 150 MHz and ePWM = 150 MHz then CLBCLK will also be 150 MHz. Side note Some older devices have a limitation of ePWM < 100 MHz. This is probably why there is /2 in the example. P65X does not have this limitation.
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