Hi Jinlong, When the Init bit ( CCCR.INIT) is cleared by your code, the MCAN module will then wait for 129 occurrences of Bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation. After the bus is recovered, the Bus-Off flag is cleared, and TX error counter is reset too. The LEC might be 5. Each time when a sequence of 11 recessive bits is monitored, a Bit0 error code is written to the Error and Status Register.
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