Part Number: MSPM0-SDK Tool/software: Hello, When reading the MSPM0Gx_TRM_revA, section "18.2.3.6 SCL Clock Low Timeout" indicates that the count that should be set in the TCNTLA register has: "Each count is equal to a timeout period of (1 + TPR) × 12 of functional clocks FCLK where the TPR is the programmable timer period" However, the driverlib and register map (Table 19-32) instead say that for Timeout counter A: "Each count is equal to 520 times the timeout period of functional clock". These seem to be contradictory as both calculations would give different results, where additionally if we were to use the calculation provided in the register map, this would ignore the frequency of the peripheral clock (i.e. the TPR component). The SCL clock low timeout does indicate the BUSSCLK clock generated for the timeout counter runs irrespective of the programmed I2C speed but i'm not sure whether that's a bit of a red herring. Any assistance on whether I'm mis-interpreting this or what calculation I should be following would be appreciated. Kind regards, Gerard
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