Can you please answer/send the following:
1.) Schematic. If you do not want to post here, I will send you an email to the address you registered with for you to respond to. At a very minimum, the linear regulator or specs for what provides power to Vdd/a and the value of the capacitor filter that is on LDO pin.
If the correct LDO and/or an undersized linear regulator is used to supply Vdd/a, then you can end up with a LDO fail or lock up issue. The LDO will appear to be at 1.2V, but the internal logic will hang and appear to the end user as a failure to operate or program/erase. The supply to Vdd/a should be capable of supplying an output current of at least 250mA. There is an inrush current that occurs at power on, if it is not adequately compensated for it can cause the Vdd level to drop, and if the LDO capacitor is not within the specified parameter of 1.0 to 3.0uF it will current starve and lock up. The inrush, and ability to handle out- of- spec LDO filter is VERY process dependent. This means, in production lines it shows up as a “bad lot.”
2.) You mention you are programming with a boot loader. Can tell me if it is a ROM invoked boot loader? or a custom written one that resides in flash? Which boot loader is being used? i.e. SSI, UART, etc.? If you are using a custom one that resides in flash, how is it programmed?
3.) Oscilloscope plot of Vdd/a rise from 0V to 3.3V at power-on.
4.) If you are using a custom written boot loader, what is your system clock setting (MOSC or PIOSC)? System clock speed?
5.) Your statement that slowing or speeding up the clock does not make a difference…and JTAG appears to be OK is interesting. Can you program with JTAG and the problem go away?
Once I have the above information, I'll be able to determine the likely cause of your issue or at the very least start the process of further debug analysis.
Lela
