Despite trying different configurations, I'm unable to attach the debugger to the device while it's running.
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Forum Post: RE: TMS320F28377D:Reason why timer stops
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Forum Post: RE: AM2634: CCS Compiler error (v12.8.1)
In addition, the CCS ti-cgt-armllvm_4.0.0.LTS error has been resolved
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Forum Post: RE: AM2432: Example of R5F Memory ECC single and double bit error injection.
Hi Potturu Here is the English translation based on your requirements: I followed the guidance provided in the post and performed a DCache fault injection test, uncovering these issues: 1、During the injection process, writing 0x28 to address 0x3f00d014 was ineffective. 2、Upon completion of execution, an ESM interrupt is triggered but fails to exit; it instead loops in this location, comparing register values as follows. 3、In an attempt to correct this issue by writing 0 to the location after entering the interrupt program via address 0x3f00d014, I found that these writes were still ineffective. Moreover, I did not locate register 0x3f00d014 in the AM2432's TRM . . Please help me understand what might be causing these issues. Thanks Jimmy
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Forum Post: RE: TMS570LS1224: SPI Pin Control Register bits 16 and 24
Thank you for responding to my question so promptly.
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Forum Post: RE: TMS320F280039C: DCAN Bootloading
Hi Skylar Confirmed. The HCLK frequency is running at 120MHz. I am starting to suspect that there might be an error with the .cmd file I am using. I am using the 28003x_generic_ram_lnk.cmd file. Would cause a problem?
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Forum Post: TMDS243EVM: MCU-PLUS-SDK-AM243X: PCIe access exception handling
Part Number: TMDS243EVM Tool/software: Hi Ti expert, I am using AM243X EVM board as RC to access FPGA EP. Now I am focusing on how to do the access exception handling. I carry out the following tests. 1 Cross border access -- I read an address that out of the range of EP' memory, the MCU crashed (The program jump to CSL_secProxyIpfeatEncodeRevVals() and stuck there, as the picture below shows). 2 Access while the EP is absent -- after initialization and RC could access EP, then power off the EP. If the RC access EP then, the MCU will crash too, the same as the result of the former test. For Cross border access, I might check the address before access. So, it is easy to avoid. My question is for the second, How can RC know the EP is active or not before any access? Check some register like LtssmState? Or as "12.2.2.4.4.6.3 Link down Interrupt" of the TRM says there will be a PCIE_LINK_STATE_PULSE interrupt when disconnection occurs, how could I enable this interrupt? Thanks and BR Chunyang
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Forum Post: RE: MCU-PLUS-SDK-AM243X: PCIe access exception handling
Close this one, open the following https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1428789/tmds243evm-mcu-plus-sdk-am243x-pcie-access-exception-handling Thanks
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Forum Post: MSPM0G3507: Not able to flash application file through BSL invocation for target microcontroller through XDS110 present on launchpad
Part Number: MSPM0G3507 Other Parts Discussed in Thread: UNIFLASH , Tool/software: Hello All, Currently I am trying to flash application.hex file through BSL invocation for target microcontroller. I have connected PA10,PA11,PA18, RESET, VCC and GND pins to the target PCB., apart from this I have connected SWCLK and SWDIO pins also at J101 and J101 is made open from on chip MSPM03507 through the TI GUI (MSPM0_BSL_GUI) which is present in SDK, I am able to flash application.txt file through BSL -> Successful But with Uniflash, not able to flash. I have selected MSPMG3507 in bootloader and given demo application and default password files.COM ports are properly set to relevant ports. but I get below error while trying through Uniflash volume_down Verbose Clear Close [INFO] CORTEX_M0P: MSPM0G3507(Bootloader) [INFO] CORTEX_M0P: Invoking Bootloader.... [INFO] CORTEX_M0P: [ERROR] CORTEX_M0P: [ERROR_MESSAGE]Failed to receive expected data! Anybody knows how it can been done through Uniflash, since we need to use hex format of application file Note: Uniflash version is 8.7.0 Regards, Prerana
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Forum Post: RE: AM2634: CCS Compiler error (v12.8.1)
Hi, Can you please tell me which SDK version are you using?
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Forum Post: RE: AM2634: CCS编译器错误（v12.8.1）
Which MCU PLUS SDK version are you using?
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Forum Post: RE: AM2634: CCS Compiler error (v12.8.1)
Both are the default SDK versions of the CCS
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Forum Post: RE: AM2634: CCS编译器错误（v12.8.1）
mcu_plus_sdk_am263x_10_00_00_35
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Forum Post: RE: AM2432: Example of R5F Memory ECC single and double bit error injection.
Hello Jimmy, [quote userid="610902" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1424164/am2432-example-of-r5f-memory-ecc-single-and-double-bit-error-injection/5474822#5474822"]Regardless of whether it's ATCM or DCACHE, any attempt to insert a double-bit error will result in a data abort.[/quote] Yes, your understanding is correct. [quote userid="610902" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1424164/am2432-example-of-r5f-memory-ecc-single-and-double-bit-error-injection/5474822#5474822"]R5 ECC automatically corrects single-bit errors without requiring manual intervention.[/quote] That is correct. [quote userid="610902" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1424164/am2432-example-of-r5f-memory-ecc-single-and-double-bit-error-injection/5477028#5477028"]3、In an attempt to correct this issue by writing 0 to the location after entering the interrupt program via address 0x3f00d014, I found that these writes were still ineffective. Moreover, I did not locate register 0x3f00d014 in the AM2432's TRM .[/quote] You have to use the below code for clearing the 0x14 offset register // Add the below code inside the ISR/Abort Handler whenever an ECC error is detected // if error == R5F Cache ECC Error { uint32_t *ptr3=(uint32_t *)0x3f00d014; // ECC Ctrl Reg *ptr3=0x0; uint32_t *ptr5=(uint32_t *)0x3f00d008; // ECC vector Reg *ptr5=0x148000; while(((*ptr5>>24)&0x1)!=1) // Polling the Read done bit to ensure ECC aggr. gets properly updated { ; } //} You will be able to come out of the ISR only after the 0x3f00d014 register gets set to 0. This will stop the error injection. 0x3f00d000 is the base address of Wkup R5 ECC Aggr. You can find the description 0x14 and 0x8 registers offsets below : Regards, Nihar Potturu.
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Forum Post: RE: RM44L920: Flash and SRAM 2Bit ECC tests fail
Hi Ilija, I mean we can also extract the part of the code in SDL, so i am suggesting you copy the .c and .h files related to these tastings and try to create a new project. In this way we can simplify the project and can easily debug if anything not working in corresponding testing. -- Thanks & regards, Jagadish.
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Forum Post: RE: TM4C1290NCPDT: TM4C1290NCPDT
Hi George, I'm sorry, I have to retract my answer. I noted that the .hex file is correct on the block number side (and the relative addresses), but it is not correct on the endiannes: Hex file: It differs from the .bin file: And if I flash the .hex file it doesn't work. If I flash the .bin it works properly. I didn't find any option in the Arm Hex Utility in order to change the byte order. I searched for it also in the SPNU118U document. These are my flags set: Do you have any suggestion about that? Thanks and regards. Diego Greco
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Forum Post: RE: TM4C129ENCPDT: XDS110 erase error
Hi, Can you try the unlock command on a LaunchPad? This is to make sure the dbgjtag.exe is running fine. How many custom boards do you have? Can you also try the unlock command on other boards you have? If all of them are having the same problem when you try to connect then I think you have a hardware problem. Has the custom board have any firmware in it before the problem occurs? If there is already firmware in the device, do you remember what was in it? The device cannot be connected If the prior code puts the device is some type of low power mode (e.g. deep sleep or hibernate) where the clock is turned off to the device without a mechanism to wake up the device. Without clock, the device is unable to synchronize with the debug probe. I want to also give you a heads up. I'm currently OOO and my response will be very much delayed.
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Forum Post: RE: AM2432: Example of R5F Memory ECC single and double bit error injection.
Hi Potturu I cleared the value at address 0x3f00d014 in the interrupt handler, now it is 0, but I am still entering the interrupt handler continuously. When ESM0_CFG:CFG_HI_PRI's LVL is not set to 0xFFFF, it becomes impossible to exit the ESM processing routine. In addition, if it's not an injected DCache fault, would normal faults require clearing the 0x3f00d014 register? Normally, such events trigger only once. Please help me. Thanks Jimmy
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Forum Post: RE: MSPM0L2228: How to Send I2C Start Condition, Stop Condition
You can decide if the MSPM0 to generate start or stop automatically but when you enabled it, the start condition will followed the address information and the stop condition generate will depends on the MBLEN. It seems it can not just generate the start condition or stop condition independently.
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Forum Post: RE: TM4C129ENCPDT: XDS110 erase error
Hi, thank you for the feedback! I'll route your question to the customer and give you a feedback as soon I receive it! No problem about answers delayed! Regards,
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Forum Post: RE: MSP-FET: MSP-FET Rev 2.0.6 - Unable to perform Corrupted Firmware Recovery (Exit Code: 49)
Hi - yeah we don't have any Windows 10 machines on site, as IT policy say we have to keep updated to latest versions of everything. I managed to take the programmer home and sort out on my personal PC and appears to behave. Would be beneficial if there was a Windows 11 workaround for other companies who have similar IT policies. Regards, Andrew
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