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Forum Post: RE: MSPM0G3507: Code not getting loaded with external oscillator

October 11, 2024, 2:32 am
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Hi, We haven't encounter this issue on MSPM0G3507 devices. Do you mean that when the MCU is running at 80MHz, you will observe issues when you try to program the MCU? And it should not related what kind of application code you are programming to the MCU, right? Best regards, Cash Hao
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Forum Post: RE: MSPM0G3507: ADC Sample time never changes total ADC conversion time

October 11, 2024, 2:40 am
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Hi, Can you share the configuration of ADC module on your project? I tried on my side. I modified the sample time and the total conversion frequency changes accordingly as expected. Best regards, Cash Hao
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Forum Post: RE: MSP430F5659: ATSAMD51J19A-AU Alternativew

October 11, 2024, 2:45 am
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Hi, I do not think the MSP430 device will be a perfect alternative for ATSAMD51J19A-AU which is a Cortex®-M4 processor with Floating Point Unit (FPU). Since I am coming from MSP department. the closest one should be MSPM0G3507 which is a Cortex®-M0+ MCU. You can check on if it can match your requirements. Best regards, Cash Hao
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Forum Post: RE: MCU-PLUS-SDK-AM243X: DDR4 Test Fail

October 11, 2024, 2:48 am
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Hi James, May I know any clue you could find from the register dump? Many Thanks! Kevin
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Forum Post: RE: MSP430FR5962: MSP430 SPI Communication question

October 11, 2024, 2:52 am
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Hi, I saw the original post. And since your latest response is just one day ago. Let's give him some time to response. Thanks for your understanding. Best regards, Cash Hao
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Forum Post: TMS320F28034: uniflash can not CONNECT with c2000

October 11, 2024, 2:55 am
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Part Number: TMS320F28034 Other Parts Discussed in Thread: UNIFLASH Tool/software: Hi experts: My customer need to use uniflash to connect with F28034 and they meet the issue as follows: If he use "Create the session From existing Target configuration file" he will meet: if he use "Detected devices" or "New configuration" he will meet: However, My customer can use this ccxml file to connect to the F28034 by using CCS. And we check the connection in CCS. The JTAG connection is OK. On my side, I test the ccxml file, and I can connect to the device by using uniflash. Any suggestions for this issue? Details for my customer's PC and software PC: windows 11 home 23H2 OS version: 22631.4317 Uniflash: 8.5.0 and 8.8.0 (Both of them meet the issue before)
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Forum Post: RE: MSP430F2418: inquiry for operation voltage and clock.

October 11, 2024, 2:59 am
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Hi, According to the figure you shared. When MCU is running at 16MHz. The supply voltage should be from 3.3V to 3.6V. Over spec behavior could cause unexpected MCU resets. Best regards, Cash Hao
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Forum Post: RE: MSP430F5503: SPI RX Problem

October 11, 2024, 3:06 am
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I have now found out that when the error occurs, the SPI interrupt triggers after the 7th rising clock edge. When it works, it behaves as expected and triggers after the 8th rising edge.I can't explain why it changes.
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Forum Post: LAUNCHXL-F28P65X: LAUNCHXL-F28P65X - compatibility with AM2BLDCSERVO ??

October 11, 2024, 3:22 am
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Part Number: LAUNCHXL-F28P65X Tool/software: Is it possible to hook up a P659-Launchpad onto a AM2BLDCDCSERVO -board? If not, what changes would be necessary? rgds
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Forum Post: RE: MCU-PLUS-SDK-AM243X: Which DP83826 signals are needed for EtherCAT

October 11, 2024, 3:36 am
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Hi Steve, I'm not really sure if ACT and CRS connections are required for EtherCAT DubDevice. I'll look into this and get back to you by early next week. Regards, Aaron
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Forum Post: RE: TM4C1294NCPDT: timer interrupt question

October 11, 2024, 3:45 am
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Hello, I have inserted the following code segment into Configure Timer block. TimerIntRegister(TIMER0_BASE, TIMER_A,Timer0IntHandler); and it does not stucks at interrupt rutine. Thanks to your helps
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Forum Post: RE: EVM430-FR6047: Calibration and hardware design issues

October 11, 2024, 11:11 pm
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Never mind. I see your email. Let's discuss on that email.
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Forum Post: RE: MSP430FR5969: PUSHX.A imm20 fails?

October 11, 2024, 11:26 pm
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Hi David, Dose it happen with TI compiler? Like v21.6.1.LTS? Could you help to share a simple project to me to reproduce this issue? I can try it on myside.
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Forum Post: RE: EVM430-FR6047: Where to submit the schematic, ask a TI expert to help review it

October 11, 2024, 11:35 pm
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Hi Zoey ,can you give us your email ? we send the schematic to you
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Forum Post: RE: EVM430-FR6047: Where to submit the schematic, ask a TI expert to help review it

October 11, 2024, 11:41 pm
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Forum Post: RE: AM2634: interrupt high latency when used freertos

October 11, 2024, 11:46 pm
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Hello, please have a look at my reply, thank you ~
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Forum Post: TMS320F28375D: Data computation problem

October 11, 2024, 11:47 pm
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Part Number: TMS320F28375D Tool/software: Hi E2E, When we use the TMS320F28375D. We ran into a situation in our operation that didn't meet our expectations. When we multiply a number(ACR_Ki) by 0(ACR_Err) and divide by 16,384, we get a negative number(-4116) What's the reason? Did we write the code wrong?
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Forum Post: AM2432: Diagnostic measures for the software readback of written configuration

October 11, 2024, 11:57 pm
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Part Number: AM2432 Tool/software: Hi We are implementing security diagnostics for the CBASS and R5F modules, which involve the 'Software Readback of Written Configuration' diagnostic procedure. However, when utilizing these features, we did not perform additional configurations on the registers of these two modules, hence making it impossible to execute this diagnostic procedure. During the initialization phase, we carried out a 'Periodic Software Readback of Configuration Registers' diagnostic measure. Could this replace the 'Software Readback of Written Configuration' diagnostic measure? Thank you Jimmy
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Forum Post: AM2431: SDDF not working in ICSSG1 PRU1

October 12, 2024, 12:26 am
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Part Number: AM2431 Tool/software: Hi, I am trying to use SDDF based on single_chip_servo_am243x-lp_r5fss0-0_nortos of motor control SDK. In the example, the SDDF is ICSSG0 and PRU0. And on my board it is ICSSG1 PRU1, the chip is AM2431-ALV. So the issue is that gSddfChSamps stays 0 and rtuSddfIrqHandler is never triggered after the initialization. The modification is as follows, 1. mclk_iep_sync.c e2e.ti.com/.../mclk_5F00_iep_5F00_sync.c In this file all CSL_PRU_ICSSG0_IPE0_BASE is changed to CSL_PRU_ICSSG1_IEP1_BASE. // Set SYNC0/1 high pulse time in iep clok cycles ( 7 clocks for 20 MHz at 300 MHz iep clk) //HW_WR_REG32(USED_IEP_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC_PWIDTH_REG, 0x0006); // Set SYNC0/1 high pulse time in iep clok cycles ( 5 clocks for 20 MHz at 200 MHz iep clk) HW_WR_REG32(USED_IEP_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC_PWIDTH_REG, 0x0004); // Set SYNC0/1 period ( 15 clocks for 20 MHz at 300 MHz iep clk) //HW_WR_REG32(USED_IEP_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC0_PERIOD_REG, 14); // Set SYNC0/1 period ( 10 clocks for 20 MHz at 300 MHz iep clk) HW_WR_REG32(USED_IEP_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC0_PERIOD_REG, 9); Clock is also updated because the base clock and IEP clock is changed to 200Mhz. PRG1_PRU1_PGI16(V12) can successfully output 20Mhz clock. 2. sddf.c e2e.ti.com/.../sddf.c In this file function initSddf, the defualt value of ecap_divider is changed to 9 for 20Mhz output based on 200Mhz clk. pruicssIep is changed to IEP1 hSdfm->pruicssIep = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->iep1RegBase); 3. single_chip_servo.c e2e.ti.com/.../single_5F00_chip_5F00_servo.c In this file I removed all endat related code. ICSSG and PRU is changed to ICSSG1 PRU1. /* Test ICSSG instance ID */ #define TEST_ICSSG_INST_ID ( CONFIG_PRU_ICSS0 ) /* Test ICSSG slice ID */ #define TEST_ICSSG_SLICE_ID ( ICSSG_SLICE_ID_1 ) /* Test PRU core instance IDs */ #define TEST_PRU_INST_ID ( PRUICSS_PRU1 ) #define TEST_RTU_INST_ID ( PRUICSS_RTU_PRU1 ) /* R5F interrupt settings for ICSSG */ #define ICSSG_PRU_SDDF_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG1_PR1_HOST_INTR_PEND_3 ) /* VIM interrupt number */ #define ICSSG_RTU_SDDF_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG1_PR1_HOST_INTR_PEND_4 ) /* VIM interrupt number */ #define ICSSG_TX_PRU_SDDF_INT_NUM ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG1_PR1_HOST_INTR_PEND_5 ) /* VIM interrupt number */ IEP clock is changed to 200Mhz /* Test Sdfm parameters */ SdfmPrms gTestSdfmPrms = { 200000000, /*Value of IEP clock*/ 20000000, /*Value of SD clock (It should be exact equal to sd clock value)*/ 0, /*enable double update*/ 10, /*first sample trigger time*/ 0, /*second sample trigger time*/ APP_EPWM_OUTPUT_FREQ, /*PWM output frequency*/ {{3500, 1000}, /*threshold parameters(High, low )*/ {3500, 1000}, {3500, 1000}}, {{0,0}, /*clock sourse & clock inversion for all channels*/ {0,0}, {0,0}}, 15, /*Over current osr: The effect count is OSR + 1*/ 64, /*Normal current osr */ 0, /*comparator enable*/ (uint32_t)&gSddfChSamps /*Output samples base address*/ }; In function init_sddf, CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE is changed to CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE /* Configure g_mux_en to PRUICSS_G_MUX_EN in ICSSG_SA_MX_REG Register. */ HW_WR_REG32((CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE+0x40), PRUICSS_G_MUX_EN); The rest is PWM related changes. The PWM interuppt App_epwmIntrISR can be entered normally, and PWM output stays 50%. Thanks, Jianyu
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Forum Post: RE: MCU-PLUS-SDK-AM263PX: Power Estimation tool doesn´t work

October 12, 2024, 12:57 am
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Hello, Could you please clarify what do you mean by "not working"? Are you changing the inputs and do not see any change in the result fields C37, D38..? If yes, which inputs did you change? I see it working on my end, hence need this clarification on what is breaking for you. Thanks, Sahana
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