Hello Simon, Our next best option is to try to do a design simulation of your code. Are you able to share a .out file that we can use to investigate? Thanks, Ibukun
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Forum Post: RE: TMS320F28388D: NMI by uncorrectable Error in CM
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Forum Post: RE: TMS320F280041C: Why would the project be changed to RTSC ?
Hi Allison, Thanks for your reply. The C2000ware is installed on both PCs. The files are both locaed on disk D, and the filepaths are exatcly the same. I try to remove the XDC tools in the ti folder. Indeed, this unusual issue is hard to locate the source and explain clearly. So, my question is: is it possible to change the project property from RTSC to normal? Best regards, Jiaxing
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Forum Post: RE: AM2431: After changing the OS, the DDR memory fails to read/write correctly.
By the way The compiler i use is ARMDS
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Forum Post: RE: TMS320F280039C-Q1: FLUNCERR caused device reset
Hello Julia, Does the customer have an NMI handler in their code? When an ECC error occurs, it should trigger an NMI and it should end up in the handler. In this handler they should be able to look at FLASH_ECC_REGS and find out what address is causing the error. The reset happens if the NMI watchdog is not serviced after the interrupt happens. Another question I would have is -- is the customer using the Flash API to program anything to the Flash during runtime? If so, we would need to review that code to make sure ECC is getting correctly programmed. In addition, a common cause of Flash corruption/errors is a sudden power interruption while a Flash program or erase operation is in progress. Best regards, Ibukun
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Forum Post: RE: EVM430-FR6047: Calibration and hardware design issues
Hi, I received the email. Going to close this thread. Best regards, Cash Hao
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Forum Post: RE: AM2634: AM263x System Reset Issues After Debugger Connection
Hello, Could you please confirm if you're using the below System Reset option in CCS to perform the reset in both the cases? Thanks, Sahana
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Forum Post: RE: LAUNCHXL-F28P65X: syscfg unser manual
Hi Aswin, thanks for your info. I want to study more about the freeRTOS, but I can't find detail description on C2000 SysConfig Overview (ti.com) . Do you have the user guide such like:
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Forum Post: RE: TMS320F28P650DK: The questions of F28388D migration.
Vivek, F2838x supports PERCNF1 register and users should configure USB_A_PHY bit to 1, so that they can use USB function. However, F28P65x doesn't have this PERCNF1 register, so the question is that in F28P65x, customers don't need to configure this kind of bit to enable internal PHY before using USB port, is this correct please? Regards, Luke
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Forum Post: RE: TMS320F28P650DK: The questions of F28388D migration.
Luke, Yes, on F28P65x user does not need to configure any such bit. Vivek Singh
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Forum Post: RE: AM2434: A DC steady-state condition is not allowed on MCU_OSC0_XI
Hi Paul, Thank you for your quick response. That's really helpful. [quote userid="35634" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1422409/am2434-a-dc-steady-state-condition-is-not-allowed-on-mcu_osc0_xi/5451275#5451275"]There is no requirement to invert the clock source.[/quote] Understood. That's good information. The customer is still concerned about the description that " DC steady-state condition is not allowed ." Is it no problem that LMK1C1104 and LMK6CE02500 are directly connected to MCU_OSC0_XI like below ? or Should C-cut (C coupling) be needed ? Thanks and regards, Hideaki
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Forum Post: RE: AM2432: Can't lift 1 hour restriction of EhterCAT Stack even though SSC library was rebuilt
Hi Harsha, Thank you for your reply. They could lift 1 hour restriction by updating from Industrial Comm SDK 9.02.00.08 to 9.02.00.15. Thanks and regards, Hideaki
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Forum Post: RE: AM2431: Ethernet performance
Hi Larry, Let me review it and get back to you by next week. Regards Ashwani
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Forum Post: TMS320F280039C: Configuring Firmware Update Boot mode
Part Number: TMS320F280039C Tool/software: I am stuck at booting into the Firmware Update Boot Mode after programming the flash. There are a few things I would like to confirm to see if I missed anything. I have configured the DCSM Zone 1 header as suggested, which is - 1 Boot Pin - GPIO22 - BOOTDEF0 with LFU Flash 0x80000, 0x90000, 0xA00000 - BOOTDEF1 with SCI SCIATX=GPIO29, SCIARX=GPIO28 We decided for our application entry point to be at 0x92000 (for Bank 1) in the following example, therefore we have setup our linker command file as below: MEMORY { BEGIN : origin = 0x00092000, length = 0x00000002 BOOT_RSVD : origin = 0x00000002, length = 0x00000126 RAMM0 : origin = 0x00000128, length = 0x000002D8 RAMM1 : origin = 0x00000400, length = 0x000003F8 // RAMM1_RSVD : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ /* RAMLS0 : origin = 0x00008000, length = 0x00000800 RAMLS1 : origin = 0x00008800, length = 0x00000800 RAMLS2 : origin = 0x00009000, length = 0x00000800 RAMLS3 : origin = 0x00009800, length = 0x00000800 RAMLS4 : origin = 0x0000A000, length = 0x00000800 RAMLS5 : origin = 0x0000A800, length = 0x00000800 RAMLS6 : origin = 0x0000B000, length = 0x00000800 RAMLS7 : origin = 0x0000B800, length = 0x00000800 */ RAMLSx : origin = 0x00008000, length = 0x00004000 RAMGS0 : origin = 0x0000C000, length = 0x00001000 RAMGS1 : origin = 0x0000D000, length = 0x00001000 RAMGS2 : origin = 0x0000E000, length = 0x00001000 RAMGS3 : origin = 0x0000F000, length = 0x00000FF8 // RAMGS3_RSVD : origin = 0x0000FFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ BOOTROM : origin = 0x003F8000, length = 0x00007FC0 SECURE_ROM : origin = 0x003F2000, length = 0x00006000 RESET : origin = 0x003FFFC0, length = 0x00000002 /* Flash sectors */ /* BANK 0 */ FLASH_BANK0_SEC0 : origin = 0x080000, length = 0x001000 FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* BANK 1 */ FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 FLASH_BANK1_SEC2_15 : origin = 0x92002, length = 0x00DFFE /* BANK 2 */ FLASH_BANK2_SEC0 : origin = 0x0A0000, length = 0x001000 FLASH_BANK2_SEC1 : origin = 0x0A1000, length = 0x001000 FLASH_BANK2_SEC2 : origin = 0x0A2000, length = 0x001000 FLASH_BANK2_SEC3 : origin = 0x0A3000, length = 0x001000 FLASH_BANK2_SEC4 : origin = 0x0A4000, length = 0x001000 FLASH_BANK2_SEC5 : origin = 0x0A5000, length = 0x001000 FLASH_BANK2_SEC6 : origin = 0x0A6000, length = 0x001000 FLASH_BANK2_SEC7 : origin = 0x0A7000, length = 0x001000 FLASH_BANK2_SEC8 : origin = 0x0A8000, length = 0x001000 FLASH_BANK2_SEC9 : origin = 0x0A9000, length = 0x001000 FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000 FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000 FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000 FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000 FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000 FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x000FF0 // FLASH_BANK0_SEC15_RSVD : origin = 0x0AFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ } SECTIONS { codestart : > BEGIN, ALIGN(8) .text : > FLASH_BANK1_SEC2_15, ALIGN(8) .cinit : > FLASH_BANK1_SEC1, ALIGN(8) .switch : > FLASH_BANK1_SEC1, ALIGN(8) .reset : > RESET, TYPE = DSECT /* not used, */ .stack : > RAMM1 /* IMPORTANT: The FreeRTOS statically allocated stack should be allocated to this section only */ .freertosStaticStack : >> RAMM1 | RAMM0 | RAMLSx /* IMPORTANT: The FreeRTOS heap should be allocated to this section only as the C28x stack memory can be allocated in the lower 64k RAM memory only. */ .freertosHeap : > RAMLSx | RAMGS0 #if defined(__TI_EABI__) .init_array : > FLASH_BANK1_SEC1, ALIGN(8) .bss : > RAMLSx .bss:output : > RAMLSx .bss:cio : > RAMLSx .data : > RAMLSx .sysmem : > RAMLSx .const : > FLASH_BANK1_SEC2_15, ALIGN(8) #else .pinit : > FLASH_BANK1_SEC1, ALIGN(8) .ebss : > RAMLSx .esysmem : > RAMLSx .cio : > RAMLSx .econst : > FLASH_BANK1_SEC2_15, ALIGN(8) #endif ramgs0 : > RAMGS0 ramgs1 : > RAMGS0 /* Allocate IQ math areas: */ IQmath : > FLASH_BANK1_SEC1, ALIGN(8) IQmathTables : > FLASH_BANK1_SEC2_15, ALIGN(8) GROUP { .TI.ramfunc } LOAD = FLASH_BANK1_SEC1, RUN = RAMLSx, LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd), RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd), ALIGN(8) DataBufferSection : > RAMM1, ALIGN(8) } -l FAPI_F28003x_EABI_v1.58.10.lib And we used the HEX2000 build tool with -b option to output in binary format. Attached are the resultant .map and .bin files. I am assuming that the .bin file is a continuous stream of bytes that are to be programmed from 0x91000 (Bank 1) since we defined .cinit to start from bank 1 sector 1 in the linker file whereas codestart is relocated to 0x92000. Upon successful flash programming, we wrote the application entry point (0x90000) with 0x92000, valid key (0x9000A) with 0x5A5A5A5A and firmware version (0x9000C) with the complement of the version number. Please refer to the screenshot below for the end result. After this step, the firmware will enable watchdog and get into a dead loop to wait for watchdog reset. Even with all these, it does not boot into the new firmware. We would like to seek your advise on what we can look at for further troubleshooting.
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Forum Post: RE: AM2434: How to set Interrupt Priority
One more question, is it possible to unified these interrupts ? Can one interrupt control both ch1 and ch2 ? For example, pruEncoderIrqHandler executes both processing of ch1 and ch2. Thanks and regards, Hideaki
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Forum Post: RE: AM2634: RPRC format will be deprecated from SDK 11.0.
Hi ?? ? Thank for your query allow me to get back on it by end of this week.
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Forum Post: RE: AM2634: OTP Keywriter Build Failing to Boot from QSPI with MCU+ SDK 09.01
[quote userid="387520" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1422402/am2634-otp-keywriter-build-failing-to-boot-from-qspi-with-mcu-sdk-09-01/5453233#5453233"]OpenSSL 1.1.1 was discontinued, I'm not sure if we're able to switch back to an outdated version.[/quote] I know dominic, apologies for this. I can share the open ssl 1.1.1 version if you want to test this
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Forum Post: TMS320F28377S: F28377 GND use problem？
Part Number: TMS320F28377S Tool/software: Use TMS320F28377S and datesheet to mark analog pin 17/35/36 and digital pin 101. Simply using a multimeter to test this chip, analog PIN17 and PIN35 are compatible with digital PIN101, while analog PIN36 is incompatible with digital PIN101. Can I only use one analog PIN36 when using this chip? Other analog ground PIN17 and PIN35 can only be used as digital ground because they communicate with digital ground PIN101. Or is there any recommendation for digital and analog use?
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Forum Post: RE: AM2634: OTP Keywriter Build Failing to Boot from QSPI with MCU+ SDK 09.01
e2e.ti.com/.../WIP_5F00_AM263x_5F00_OTP_5F00_Keywriter_5F00_Steps.pdf Also please refer to this on detailed steps for OTP Keywriter provisioning.Let me know if you have any other questions.
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Forum Post: RE: TMS320F28379D: TMS320F28379D
Hi, No you cannot. I recommend XDS100v2, XDS110, or XDS200. Best Regard, Ben Collier
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Forum Post: RE: TMS320F28015: Issues Connecting TMS320F28015 with XDS110 in UniFlash and CCS 12
Hi, I apologize for the delay, I will have to get back to you towards the end of this week. Best Regards, Ben Collier
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