[quote user="Charles Tsai"]You are right that you need to use the palign as illustrated in the two wiki pages.[/quote]The information on the two Wiki pages is a bit disjointed: The http://processors.wiki.ti.com/index.php/Linker_Generated_ECC page which mentions palign() doesn't contain a modified HL_sys_link.cmd file. The http://processors.wiki.ti.com/index.php/LAUNCHXL2-570LC43-RM57L:_LinkerECCRecommendation page contains a link to a modified HL_sys_link.cmd file with Linker ECC enabled. However, that page doesn't mention palign() and the linked HL_sys_link.cmd file uses align rather than palign. Perhaps the Wiki pages could be improved to avoid confusion. Also, since linker generated ECC is the recommendation for for TMS570LC4357 devices, should the template linker command files in HALCoGen be updated to use linker generated ECC and use of palign? Edit : Correct device name
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Forum Post: RE: Bus ECC ESM error signaled on TMS570LC4357 with cache enabled when read from a partially programmed cache line in flash
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Forum Post: RE: TMS570 MCU EMIF WE Signal abnormality using HalCoGen code
Nestor, You can configure the MPU inside HalCoGen . The MPU is part of the CPU System Control Coprocessor - so the documentation for it is in the ARM Cortex R4F technical reference manual and as well some is in the PMSA architecture section of the ARM Architecture manual -v7AR. Usually the HalCoGen default settings are pretty close to 'useful' (you may need to adjust the EMIF settings for this particular case, but defaults for internal memory should be useable). -Anthony
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Forum Post: RE: TIVA doensot reboot properly after upgrading it through API : ROM_UpdateUART ()
Thanks Amit. Thanks Robert. Can you please guide me as to how can I build the flash bootloader. I have the code for flash bootloader given by TI. And how can I flash the bootloader along with the application using CCS or LM Flash ? Thanks, Sanchit Mehra
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Forum Post: RE: HalCoGen/Hercules: EMIF-ASYNCH1/2/3
Hi Sarah, Sorry I am getting a bit confused and need to clarify a couple points: 1) When measuring the pulse width - which pin are you measuring? Is it the chip select or is it another pin like WE or OE? 2) By '5 pulses' do you mean 1 pulse low of width 5 clocks? Or do you mean 5 distinct pulses low, with the pin returning high between each? (and this is on the chip select pin again?) 3) 223 is a data bus value, correct? It's not 'setup of 2, strobe of 2, hold of 2'.. Just want to make sure of this. A screen capture from a scope would be really helpful here if it's possible to grab one. I don't expect any issue other than the EMIF errata (just a post today about it - and you may need to read it too... e2e.ti.com/.../516918) . Thanks and Best Regards, Anthony
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Forum Post: RE: Peripherals buffer size is not documented
I see I can resolve this question myself. Consider this thread closed.
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Forum Post: RE: HalCoGen/Hercules: EMIF-ASYNCH1/2/3
Hi Anthony, (from the EE) 1. We are measuring at nCS3. 2. By 5-pulses, I mean 5 times nCS3 goes low with the low time being 600ns and the high time being 700ns. 3. That is correct and it is a data bus value, which we read and is in decimal. Thanks, Sarah
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Forum Post: RE: TIVA doensot reboot properly after upgrading it through API : ROM_UpdateUART ()
Hello Sanchit, You can start with the example flash bootloader in TivaWare. The process of flashing the bootloader can either be via JTAG or Serial Interface. CCS shall only perform JTAG. Uniflash and LMFlash can perform either JTAG, UART or USB. Uniflash has a larger set of emulator for JTAG as compared to LMFlash. Regards Amit
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Forum Post: RE: TM4C1924NCPDT CMSIS register bit defines
Hello Andrei The same is available on GitHub. github.com/.../TI Regards Amit
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Forum Post: RE: Enabling SDRAM in CCS/Hercules/HalCoGen
Hi Charles/Chester, I modified HalCoGen as follows: I modified the sys_link.cmd file as follows: /*----------------------------------------------------------------------------*/ /* Memory Map */ MEMORY { VECTORS (X) : origin=0x00000000 length=0x00000020 FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0 FLASH1 (RX) : origin=0x00180000 length=0x00180000 STACKS (RW) : origin=0x08000000 length=0x00021000 RAM (RW) : origin=0x08021000 length=0x0001f000 /* USER CODE BEGIN (2) */ RAM2 (RW) : origin=0x80000000 length=0x01000000 /* USER CODE END */ } /* USER CODE BEGIN (3) */ /* USER CODE END */ /*----------------------------------------------------------------------------*/ /* Section Configuration */ SECTIONS { .intvecs : {} > VECTORS .text : {} > FLASH0 | FLASH1 .const : {} > FLASH0 | FLASH1 .cinit : {} > FLASH0 | FLASH1 .pinit : {} > FLASH0 | FLASH1 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM FEE_TEXT_SECTION : {} > FLASH0 | FLASH1 FEE_CONST_SECTION : {} > FLASH0 | FLASH1 FEE_DATA_SECTION : {} > RAM /* USER CODE BEGIN (4) */ .bss : {} > RAM | RAM2 .data : {} > RAM | RAM2 .sysmem : {} > RAM | RAM2 /* USER CODE END */ } Here is the built linker map output: CCMv3.map: ****************************************************************************** TI ARM Linker PC v5.2.7 ****************************************************************************** >> Linked Mon May 30 10:05:39 2016 OUTPUT FILE NAME: ENTRY POINT SYMBOL: "_c_int00" address: 0003caa8 MEMORY CONFIGURATION name origin length used unused attr fill ---------------------- -------- --------- -------- -------- ---- -------- VECTORS 00000000 00000020 00000020 00000000 X FLASH0 00000020 0017ffe0 0005047f 0012fb61 R X FLASH1 00180000 00180000 00000000 00180000 R X STACKS 08000000 00021000 00000000 00021000 RW RAM 08021000 0001f000 000050d8 00019f28 RW RAM2 80000000 01000000 00000000 01000000 RW SEGMENT ALLOCATION MAP run origin load origin length init length attrs members ---------- ----------- ---------- ----------- ----- ------- 00000000 00000000 000504a8 000504a8 r-x 00000000 00000000 00000020 00000020 r-x .intvecs 00000020 00000020 0003d8dc 0003d8dc r-x .text 0003d900 0003d900 0000ea73 0000ea73 r-- .const 0004c378 0004c378 00004130 00004130 r-- .cinit 08021000 08021000 000050d8 00000000 rw- 08021000 08021000 00004718 00000000 rw- .data 08025718 08025718 00000800 00000000 rw- .sysmem 08025f18 08025f18 000001c0 00000000 rw- .bss SECTION ALLOCATION MAP output attributes/ section page origin length input sections -------- ---- ---------- ---------- ---------------- As you can see .data, .bss, and .sysmem all still use the internal RAM exclusively and from my view the linker still does not use the SDRAM. My concern is class and malloc allocations. Thanks, Sarah
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Forum Post: Program will not fit into available memory! Is there a fix?
I'm running an simple Simulink model on a Delfino Launchpad F28377S and I get the following error: " C:/MATLAB/SupportPackages/R2016a/toolbox/target/supportpackages/tic2000/src/c28377S.cmd", line 81: error: program will not fit into available memory. run placement with alignment/blocking fails for section ".esysmem" size 0x400 page 1. Available memory ranges: RAMLS5 size: 0x800 unused: 0x39b max hole: 0x39b error: errors encountered during linking; "../test.out" not built >> Compilation failure gmake: *** [../test.out] Error 1 N:\My Documents\MATLAB\Solomon\test_ert_rtw>echo The make command returned an error of 2 The make command returned an error of 2 N:\My Documents\MATLAB\Solomon\test_ert_rtw>An_error_occurred_during_the_call_to_make 'An_error_occurred_during_the_call_to_make' is not recognized as an internal or external command, operable program or batch file. ### Creating HTML report file test_codegen_rpt.html ### Build procedure for model: 'test' aborted due to an error. Error(s) encountered while building "test": ### Failed to generate all binary outputs. This is very surprising as my model is extremely simple, so I was wondering if I was doing something wrong that results in this error. Also, I'm a complete newbie to the TI environment, so if there's a fix, it'd be much appreciated if someone can guide me through it. Thanks! Solomon
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Forum Post: RE: Enabling SDRAM in CCS/Hercules/HalCoGen
Hi Sarah, The SDRAM is memory mapped at 0x80000000. Once you call the emif_SDRAMInit() the EMIF module will take care of interfacing between the CPU and the external SDRAM. If you are just eading/writing to the SRAM then you shouldn't need to touch the linker command file. If you are going to run code from SDRAM then you need to define MEMORY and SECTION in the linker command file and also define your load and run addresses. if you want to reserve spaces in SDRAM for uninitialized variables you will also define the MEMORY and SECTION in the linker command.
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Forum Post: RE: Can I jump to sci_boot directly from an application using TMS320F28034?
Hi Santosh, After sniffing the packets with a packet sniffer I can see that all SCI_Boot does is load a program and then jump to it. It is this program that allows C2prog to output the following to do the burn (I guess it could be two programs. One to get the chip ID and rev and another to do the flash burn) Connecting with target... -Chip ID: 0xCF -Chip Rev: 0x02 OK. Unlocking target... OK. Loading... OK. Connecting with target... -Flash API version: 200 OK. Erasing flash... [ABC] OK. Programming... OK. Now the question becomes. What program? Since the output above reads a flash api version of 200. I wonder if the program C2 prog is loading the program at C:\ti\ controlSUITE \device_support\f2802x\v200\f2802x_examples\flash_f28027 in order to send the erase sector commands and program the flash. What program do you think C2prog is loading if it claims to be running -Flash API version: 200? When I sniff the output during the programming phase of C2prog I can see the bytes from the intel hex record get programmed. For example Output packet from C2prog captured with packet sniffer 00 3F 5F 57 A9 F1 0E E6 1E AC 56 63 00 A7 56 05 00 A7 56 8B A9 91 D0 0A 0E EE 1E AC 56 63 00 A7 56 05 00 A7 D5 A3 FC FF FE I am able to match this data from the following line of the intel hex record for example. :205F5700A9F10EE61EAC566300A7560500A7568BA991D00A0EEE1EAC566300A7560500A753 So what ever program C2prog is loading is excepting packets that take the following from It seems that every packet that programs an intel hex record line has an FF FE on the end. It also has some other data between the and In the above would you be able to say what the D5 A3 FC is? Is it some type of check sum?
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Forum Post: RE: TIVA doensot reboot properly after upgrading it through API : ROM_UpdateUART ()
Thanks Amit, And at what address should I flash the flash bootloader ? is it 0x2000.0000 ? Sanchit
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Forum Post: RE: EMIF 16-bit async. write generates multiple writes
Adrien, Can you first confirm which TMS570 device you are using? Please refer to the below errata. The silicon is fixed for this errata in the latest silicon revision if you are using TMS570LS31x/TMS570LS12x. Can you try changing to strongly-order and do you still see extra nWE pulses? If you have the TMS570LC43x device then you will have a different EMIF errata. See below. The latest silicon (revB) is also fixed for this issue. You will need to use the nDQM as a qualifier to suppress the extra WE pulses.
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Forum Post: RE: Generating a reset signal from Tiva c TMC4123 Microcontroller
Hello Robert, Yes. That could work. A fast CPLD with independent clocking/PLL tree for high frequency operation. Regards Amit
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Forum Post: RE: what is the maximum frequency ADC of 12 bit resolution can I interface with my launchpad f28377S
Hi again Basically it will not be possible to sample at 50 million samples per second. External SPI can run up to 50 MHz. Divide this with 12 (bit)you would in theory have the max. transfer rate for an external SPI ADC.
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Forum Post: RE: what is the maximum frequency ADC of 12 bit resolution can I interface with my launchpad f28377S
Thank You Gautam Iyer, but I am asking if I interface an external ADC to my launchpad than up to which sampling rate will it support and not loosing any samples.
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Forum Post: RE: EVM430-F6779 Reset Calibration
>How do i reset the calibration for the power meter to factory default? You can't unless you calibrate meter yourself or send it to factory for calibration. Hint: before you tinker with data - do some backups.
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Forum Post: RE: Using a MSP430FR2632IRGER Sample for messing around with. What additional exquipment do I need?
If you are just starting - then consider to get Launchpad instead of building one. Wiki is good resource, 43oh either. Also check C sample code which you can find in the webpage of every msp430 chip and obviously get datasheet and user's guide for chip of your choice. Then you need compiler. Code size limited IAR workbench as dev tool is my preferred choice.
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Forum Post: I2c master clock frequency setting
I am using the piccolo f28069 at 90Mhz. I checked the CPU speed at the pin GPIO18 using the scope (got 22.4Mhz with XCLKOUTDIV=0 ). I configured the I2C slock to run at 400kbit/s see code below but I got only 106kbit/s measured with the scope !!! Any Idea where can be the problem? Thank you Hamid void I2CA_Init(void) { // Initialize I2C I2caRegs.I2CSAR = I2C_SLAVE_ADDR; // Slave address I2caRegs.I2CPSC.all = 8; // IPSC = 8 Prescaler - need 7-12 Mhz on module clk CLK module = 90/(8+1)= 10Mhz //IPSC = 8 //Tmodul*[(ICLL+d)+(ICCH+d)]=Tmaster=400khz // low periode = Tmod*(ICCL+d) // High periode = Tmod*(ICCH+d) //low periode > High periode (2 time appr) //d=5 for IPSC >1 I2caRegs.I2CCLKL = 10; // NOTE: must be non zero I2caRegs.I2CCLKH = 5; // NOTE: must be non zero //I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts I2caRegs.I2CIER.all = 0x00; // disable all interrupts I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset // Stop I2C when suspended I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT, return; }
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