Hi Michael, To set up the GPIO pin interrupt can be tricky and it is not well documented either. I will forward your thread to our expert for further assistance. He is busy on some other high priority tasks. The response may be delayed. Thansk you so much for your patience! Best regards, Ming
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Forum Post: RE: AM2432: Using MCU_GPIO interrupt from main domain
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Forum Post: RE: TMS320F28377D: TMS320F28377D implementation (beginner)
Eric, Thanks for reaching out. The above will not work for interfacing the device with CCS. The FT2232 has been programmed to act as the emulator(in this case an XDS100v2) to connect the C2000 to CCS. This is taking the USB signals and creating the JTAG signals, TDO/TDI/TMS/TCK/TRSTn that the F2837xD device uses to access the test port. You should see these coming out of the isolators U5 and U7 on the schematic. While the above would allow you to interact with the on-chip USB module, we do not support a debug connection through this interface. For a more production purpose PCB I agree with eliminating the FT2232, but for debug you will need to bring the JTAG signals from the C2000 MCU to a standard header(either TI 14-pin or TI 20pin) and buy an XDS110 or XDS200 external emulator pod to connect with CCS. Let me know if I can provide more resources to get you started. You can check out the F2837xD experimenter kit, base board to see the 14-pin connection PN. Best, Matthew
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Forum Post: MSP430F5418A: [ACK_ERROR_MESSAGE]Unknown ACK value!
Part Number: MSP430F5418A Other Parts Discussed in Thread: MSP430F5418 , Hello, first things first: I used to use the device MSP430F5418 but it is not a selling part available anymore so I am changing to the MSP430F5418A device. I already updated the BSL Scripter, now I am using the version 3.4.0. I am using the following configuration in my script: SCRIPT: MODE msp430f543x UART 57600 COM4 PARITY VERBOSE MASS_ERASE TX_BSL_VERSION And when the line: " TX_BSL_VERSION " and the line: "MASS_ERASE" run I recieve back: [ACK_ERROR_MESSAGE] Unknown ACK value! Anyone has a clue of what I am looking at?
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Forum Post: RE: MSP430FR59941: CryptoBSL entry sequence failure
Hi Evan, We are waiting for a fw modification to keep TEST low and to send the described waveform. As soon as we can confirm that it works we should be good to close this issue. Thanks for your help! I will update ASAP. -Tony
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Forum Post: RE: TMS570LS3137: Actual Part Number is TMS5703137CGWTQEP
Hi AJ, I am sorry I don't know the part numbering conventions for DLA parts. The snapshot you posted is pretty blurred, I am still not clear what do -01XE or -02XE mean in the DLA part numbers. The note #6 of packaging info in device datasheet says the devices may have multiple finish options. Don't know how those options are reflected in the part #. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. You may check with sales. Can you send me a private message? I will forward your question to our marketing team (and cc to you).
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Forum Post: RE: MSP430FR6047: BSL - Mass Erase Time
Hi Shyam, Mass erase times differ by device. For the mass erase time for the MSP430FR6047, you may need to look into the datasets for the parts to find the mass erase time. As seen in SLAU319AE, mass erase times for our flash devices bootloader can vary greatly, from 17.2 ms to 206.4 ms. MSP430 Flash Devices Bootloader (BSL) User's Guide (Rev. AE) (ti.com) You may also want to refer to some of our examples from our MSP BSL webpage (linked below) under the "Embedded Programming Solutions" Section. MSPBSL Driver or library | TI.com This has some examples to work off of. There is also more helpful information in the document that you mentioned, The MSP430 FRAM Devices Bootloader User Guide (linked below). MSP430 FRAM Devices Bootloader (BSL) User's Guide (Rev. AA) (ti.com)
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Forum Post: RE: TMS570LC4357: FreeRTOS
Hi Sakti, This is a issue. When you power up the device, the CPU should be in privileged mode. You can decide to stay in this mode and execute all your code in this mode. If you want to enter user mode, you will program CPSR to switch to user mode easily. To switch from user to a privileged mode, you can use an SVC call or use a System Software Interrupt of the system module (SSI) which will generate an IRQ interrupt for you and put you into the IRQ mode. I am not sure how to do this during power-up. Are you using TI EVM? If not, can you try another board or another silicon you ordered from ti?
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Forum Post: RE: EVM430-FR6047: Help on UART example code
Hello, Can you try putting a jumper wire from JTAG_RXD (J3 block) to COMM_TXD (J1 block), and another jumper from JTAG_TXD (J3 block) to COMM_RXD (J1 block), and see if that gives you an echo? I've attached a picture to illustrate, where I have color coded the locations to connect via jumper wires. Sincerely, Kyle
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Forum Post: TMS320F280049C: Unable to sample data ADC-C Input 1
Part Number: TMS320F280049C Other Parts Discussed in Thread: DRV8320 Hello, I've searched all over the forums but can't find anything related. For some reason we are unable to sample data on ADC-C Input 1 "C1". Below is the function for setting up the ADCs. All other ADCs are working except for C1. C1 is dedicated to sampling one of the phase voltages for a BLDC drive which incorporates a DRV8320. Thank you in advance for any ideas! Best, Jonathan void HAL_setupADCs(HAL_Handle handle) { HAL_Obj *obj = (HAL_Obj *)handle; SysCtl_delay(100U); ADC_setVREF(obj->adcHandle[2], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V); ADC_setVREF(obj->adcHandle[1], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V); ADC_setVREF(obj->adcHandle[0], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V); SysCtl_delay(100U); // Configure internal reference as 1.65V*2 = 3.3V ASysCtl_setAnalogReference1P65(ASYSCTL_VREFHIA | ASYSCTL_VREFHIB | ASYSCTL_VREFHIC); // Enable internal voltage reference ASysCtl_setAnalogReferenceInternal(ASYSCTL_VREFHIA | ASYSCTL_VREFHIB | ASYSCTL_VREFHIC); // Set main clock scaling factor (50MHz max clock for the ADC module) ADC_setPrescaler(obj->adcHandle[0], ADC_CLK_DIV_2_0); ADC_setPrescaler(obj->adcHandle[1], ADC_CLK_DIV_2_0); ADC_setPrescaler(obj->adcHandle[2], ADC_CLK_DIV_2_0); // set the ADC interrupt pulse generation to end of conversion ADC_setInterruptPulseMode(obj->adcHandle[0], ADC_PULSE_END_OF_CONV); ADC_setInterruptPulseMode(obj->adcHandle[1], ADC_PULSE_END_OF_CONV); ADC_setInterruptPulseMode(obj->adcHandle[2], ADC_PULSE_END_OF_CONV); // enable the ADCs ADC_enableConverter(obj->adcHandle[0]); ADC_enableConverter(obj->adcHandle[1]); ADC_enableConverter(obj->adcHandle[2]); // set priority of SOCs ADC_setSOCPriority(obj->adcHandle[0], ADC_PRI_ALL_HIPRI); ADC_setSOCPriority(obj->adcHandle[1], ADC_PRI_ALL_HIPRI); ADC_setSOCPriority(obj->adcHandle[2], ADC_PRI_ALL_HIPRI); // delay to allow ADCs to power up SysCtl_delay(1000U); // RB2/B1 ADC_setInterruptSource(obj->adcHandle[1], ADC_INT_NUMBER1, ADC_SOC_NUMBER2); // ISENA --> B2 ADC_setupSOC(obj->adcHandle[1], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN2, HAL_ADC_SAMPLE_WINDOW); // ISENB --> B4 or C8 ADC_setupSOC(obj->adcHandle[2], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN8, HAL_ADC_SAMPLE_WINDOW); // ISENC --> C0 ADC_setupSOC(obj->adcHandle[0], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN0, HAL_ADC_SAMPLE_WINDOW); // VSENA - A2 ADC_setupSOC(obj->adcHandle[0], ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN2, HAL_ADC_SAMPLE_WINDOW); // VSENB - C1 ADC_setupSOC(obj->adcHandle[2], ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN1, HAL_ADC_SAMPLE_WINDOW); // VSENC - C2->RC1 ADC_setupSOC(obj->adcHandle[2], ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN2, HAL_ADC_SAMPLE_WINDOW); // VSENVM - B1->RB2. ADC_setupSOC(obj->adcHandle[1], ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN1, HAL_ADC_SAMPLE_WINDOW); // B3 Speed Input ADC_setupSOC(obj->adcHandle[1], ADC_SOC_NUMBER15, ADC_TRIGGER_EPWM2_SOCA, ADC_CH_ADCIN3, HAL_ADC_SAMPLE_WINDOW); return; } // end of HAL_setupADCs() function
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Forum Post: RE: TMS570LC4357: ADC10 Parity Bits memory mapping not clear
[quote userid="430202" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1108259/tms570lc4357-adc10-parity-bits-memory-mapping-not-clear/4107830#4107830"]Does the Parity Ram only support 8bit access?[/quote] Actually we can perform 8-bit access or 32-bit access from my test.. The TRM is not accurate. There is 1 parity bit for 32-bit word or 17-bit (the upper 15 bits are reserved, and won't affect the parity). I need to double check it. My test code: #define adcRAM1 (*(volatile uint32 *)0xFF3E0000U) #define adcRAM1_B0 (*(volatile uint8 *)(0xFF3E0000U + 0x3U)) #define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U)) #define adcPARRAM1_B0 (*(volatile uint8 *)(0xFF3E0000U + 0x1000U + 0x3U)) void adc_parity_test() { volatile uint32 adcramread = 0U; uint32 adcparcr_bk = adcREG1->PARCR; /* USER CODE BEGIN (61) */ /* USER CODE END */ adcInit(); adcREG1->OPMODECR &= 0x7FFEFFFF; adcREG1->OPMODECR |= 0x80010000; //12-bit (bit 31), ADC RAM Test Mode is enabled(bit 16) /* Set the TEST bit in the PARCR and enable parity checking */ adcREG1->PARCR = 0x10AU; adcRAM1 = ~(adcRAM1); //flip all the bits adcRAM1 = ~(adcRAM1); //flip all the bits back adcRAM1_B0 = ~(adcRAM1_B0); //flip the bits of least byte adcRAM1_B0 = ~(adcRAM1_B0); //flip the bits of least byte back /* Invert the parity bits inside the ADC1 RAM's first location */ adcPARRAM1 = ~(adcPARRAM1); adcPARRAM1_B0 = ~(adcPARRAM1_B0); //invert lsb adcPARRAM1_B0 = ~(adcPARRAM1_B0); /* clear the TEST bit */ adcREG1->PARCR = 0x00AU; /* This read is expected to trigger a parity error */ adcramread = adcRAM1;
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Forum Post: RE: C2000WARE-DIGITALPOWER-SDK: Can't import project from DigitalPower SDK
Hi Kevin, Were you able to import the project via the Resource Explorer (TIREX)? Can you confirm the version of C2000Ware-DigitalPower-SDK you are attempting to install. You are correct that CCS looks for the package to be installed in your local drive under the ti or ti/c2000 folders (e.g C:\ti\c2000). If it is installed in a different directory, CCS won't be able to detect that directory unless you up date the search directories to include that local directory. You should be able to view the downloading status in the tool bar if you click the clock icon located at the top on the same row as the Resource Explorer Label. It should be noted that powerSUITE no longer needs to be installed as a local product. It appears that the instructions in that user's guide are not up-to-date. I'll copy the owner for that design to confirm the accuracy of the described steps. Instead of clicking "Run" once you navigate to the specific project within TIREX, you should see the "Import" button appear on the left-hand side of the window. This will import the project in CCS and launch the GUI page. Let me know if you have any questions. Regards, Ozino
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Forum Post: RE: C2000WARE-DIGITALPOWER-SDK: CCS can't see installed DigitalPowerSDK
Kevin, I noticed you have another forum post open asking as similar question about the installation of the product. CCS should be able to auto detect the package once you've installed it at the directory specified above. Please confirm you can view this package in the TI Resource Explorer window within CCS. Regards, Ozino
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Forum Post: RE: AM2634-Q1: Can QSPI memory-map reads external Flash in 16/32 or even 64-bit?
Hi Will, I am reaching out to the experts for comments on this subject. Thanks for your patience! Best, Daniel
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Forum Post: RE: TMS320F280049C: CPU executes outside (for, while, SysCtl_delay()) loops
[quote userid="8973" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1108312/tms320f280049c-cpu-executes-outside-for-while-sysctl_delay-loops/4108134#4108134"]Can you clarify a bit if you think this is a issue effecting program execution or one that effects the state of watched variables during debug when BPs are inserted in the code?[/quote] Condition occurs without inserted break points or CCS real time debug being enabled. Oddly my UART peripheral application with modifications for SCIB use the same (for/while) loops that work correctly via TM4C1294 though have major issues with C++ functions via x49c. Mostly relative to SCIB RX/TX FIFOs versus UART FIFO's of the TM4C1294 ARM cortex that have no such issues with stopping forward processing of C++ syntax after the function ( } ). The examples of the for while SysCtl_delay() were posted above to insert into added PIE interrupts of group1/9 with Instaspin SDK (FOC) being loaded. Only do we see debug single stepping (F5) cursor jump to the next function after the last functions return ( } ) mnemonic. The actual firmware (*.out) during debug (RUN) mode should never behave this way especially when break points were not set. So it could be the XDC110 debug emulation doing this jump as I think you seem to be suspecting?
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Forum Post: RE: TMS320F280049C: CPU timer 0 interrupt occurs faster than SYSCLK
[quote userid="48581" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1107677/tms320f280049c-cpu-timer-0-interrupt-occurs-faster-than-sysclk/4106765#4106765"]Still SCIB RX_INT3 is to even respond and the LED blink rate (2750hz) inside ADCA1 interrupt handler never blinks, stays on. [/quote] That was partly due to of all things a variable defined (unsigned char) versus (uint16_t) that works great via the same firmware TM4C1249 MCU with same compiler version. Regarding x49c interrupt groups with core priority order values: Handling multiple Interrupts withing groups breaks down with Instaspin SDK (FOC). It severely impacts motor commutation groups1/9 priority order chopping into ADCA1 interrupt via CPUTimer0. Perhaps XDC110 emulation may be effecting PIE core interrupt priority with or without real time debug being enabled? Yet when launch pad is released form debug the same ADCA1/ADCA2 chopping interrupt condition occurs with CPUTimer0 asserting outer ring functions to display small parts of the same data visible in the debug watch window *.js script file variables. Oddly SCIB RX FIFO mandated me to change simple (for) count variable (unsigned char) to (uint16_t) for RX FIFO to load any input data (MyArray[i]) at all. There are several issues within PIE interrupt module specifically the core priority order seems very broken R3 silicon. I say that being Instaspin FAST estimator should be able to accept other PIE interrupts without impacting motor commutation. Otherwise it is a failed MCU for any automotive or industrial applications that require multiple interrupts without copping FAST estimator motor commutation data into unusable shreds. The small motor rotor literally stops and jumps up to speed each interrupt cycle of Timer0. The bigger motor rotor sounds like 1942 V2 rocket propulsion system :-)...
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Forum Post: MSP430F67471A: BSL TEST and RST pin polarity
Part Number: MSP430F67471A Other Parts Discussed in Thread: TEST , I am attempting to load firmware onto the MSP430F67471A using the provided (factory programmed) UART BSL. My understanding is that the RST and TEST pins need to be toggled in the correct sequence to start the BSL. Below is the sequence from the MSP430 Flash Devices Bootloader (BSL) User Guide. The red text indicates the MCU pins these signals are connected to on my PCB. \ In the sequence above, the pattern to the right of the red TEST and RST text appears to be correct, but there is no response from the BSL. When TEST is inverted as shown above, I receive error messages from the BSL (0x52 checksum incorrect and 0x51 incorrect header) which seems to indicated that the BSL is being activated. Why does it appear that TEST needs to be inverted to activate the BSL? I am using python-msp430-tools to generate the signals above and I am unsure why the signals toggle like they do to the left of the red text in both images but that may be part of the issue. Also, I believe the checksum and incorrect header errors are not related to this issue and will need to be debugged separately. If someone thinks otherwise, please let me know. Thanks for the help.
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Forum Post: RE: AM2432: MII / RGMII for industrial communication, and RMII / RGMII for cpsw
Hi Dhaval, Thank you for your kind explanation. I have a quick question from a bit different angle regarding PRU firmware. As we discussed in the meeting before, you may remember that a custom EIP stack on top of Lwip will run in our product. This custom stack will not use any APIs or features provided by TI EIP PRU firmware, and it will use only Lwip APIs. So, I was wondering if there is a simpler way which we can implement to use the Ethernet network ports (2 port switch mode). For our case, do you think that we still need to implement the same steps you described? Or can we skip some steps like TimeSync or DLR for our case? I also wonder if there is a way even not to use PRU firmware for ethernet communication. I would appreciate it if you share your experience and guide on this again. Best, Moonil
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Forum Post: TMS320F28335: Hardware compatibiity of TMS320F28335 controlCARD and TMDSCNCD28035ISO control card
Part Number: TMS320F28335 Other Parts Discussed in Thread: TMDSCNCD28035ISO , I have purchase TI Solar Micro-inverter Reference Design, this design uses C2000 Solar Micro Inverter EVM kit where TMDSCNCD28035ISO control card is to be used with the base board. I wish to use TMS320F28335 controlCARD instead and insert this control card into the base board. Then re-do the software again for control of this Solar Micro Inverter in order to fully understand how to do this for 28335 MCU. Is it possible ? My question is TMS320F28335 pin compatible with TMDSCNCD28035ISO from hardware point of view, such that I can just swap it out. I understand that I would need to change memory maps, cmd files etc but can re-use some parts of existing code. Just like to confirm it before I try it out. Thanks and regards
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Forum Post: TMS320F28035: 28035 dead-time question
Part Number: TMS320F28035 Hi, TI expert: now i found a dead-time question of PWMxA and PWMxB output in my project which using TMS320F28035. i config like this: pEpwmRegs->AQCTLA.bit.CAU = AQ_CLEAR; pEpwmRegs->AQCTLA.bit.CBU = AQ_SET; // set actions for EPWM1A-M3 pEpwmRegs->AQCTLB.bit.CAU = AQ_CLEAR; pEpwmRegs->AQCTLB.bit.CBU = AQ_SET; // set actions for EPWM1A-M3 pEpwmRegs->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // S1=1,S0=1 all enable pEpwmRegs->DBCTL.bit.POLSEL = DB_ACTV_HIC; // S3=1,S2=0 EPWMxB invert pEpwmRegs->DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; // S5=1,S4=0 pEpwmRegs->DBFED = 7; pEpwmRegs->DBRED = 7; pEpwmRegs is pointer to PWM1, and i hope PWM1A and PWM1B is complementary waves and have 7 cnt dead-time. but when enable PWM1A,PWM1B output, i find the rise dead-time is 100ns and the drop dead-time is 135ns like the delay time is not same , but you can see all both PWMxA and PWMxB delay time config is 7, when i changed the config like this: pEpwmRegs->DBFED = 6; pEpwmRegs->DBRED = 8; and the dead-time of PWMxA and PWMxB are same ,both 116ns. i don't know why, please help me, tks!
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Forum Post: RE: TM4C1294KCPDT: WatchDog timer -TM4c1294KCPDT
Jacobi, [quote userid="189615" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1108599/tm4c1294kcpdt-watchdog-timer--tm4c1294kcpdt/4108555#4108555"]Can you load any projects into the device? If yes, please see the second set of questions.[/quote] Yes, I can download project into the device. My aim is to be add watchdog timer concept into my application code to reset the device. After adding as such, watchdog interrupt is cleared every one seconds once.When i try to reset the device by blocking watchdog interrupt clear set as variable Zero .As that time getting error as mentioned above . [quote userid="189615" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1108599/tm4c1294kcpdt-watchdog-timer--tm4c1294kcpdt/4108555#4108555"] If you are able to load programs, what are you doing that prompts that error? Have you tried to, after a reset, reconnect to the core without breaking the debug session? Are you able to get access to any of the device registers? [/quote] I can able to load program . Tried many time after reset and reconnect the device ,but forcing to block watchdog timer interrupt clear getting error instead of device get reset. Best regards, Rani
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