Part Number: TMS570LS3137 Hi Team, In map clocks configuration, why vclk4 is set ON (from halcogen), even though controller doesn't support vclk4? *sys1_cddis = (Uint32)(((Uint32)0U << 4U ) /* AVCLK1 ON */ | (Uint32)((Uint32)0U << 5U ) /* AVCLK2 ON */ | (Uint32)((Uint32)0U << 8U ) /* VCLK3 ON */ | (Uint32)((Uint32)0U << 9U ) /* VCLK4 ON */ | (Uint32)((Uint32)1U << 10U) /* AVCLK3 OFF */ | (Uint32)((Uint32)0U << 11U)); /* AVCLK4 ON */ Also, in map clocks, Why do we need to set bit 8 (Which is a reserved as per spnu499c.pdf) to 1? *sys2_clk2cntl = (*sys2_clk2cntl & 0xFFFFF0F0U) | (Uint32)((Uint32)1U << 8U) | (Uint32)((Uint32)8U << 0U); Thank you, Baba.
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Forum Post: TMS570LS3137: CDDIS Register settings
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Forum Post: CCS/TMS320F28377S: TMS320F28377S
Part Number: TMS320F28377S Tool/software: Code Composer Studio As mentioned in the document which also has been attached to the mail. It has been mentioned that document 10 examples have been provided for the DCAN. How can I have all the examples iin .c files. I especially need the "can_ex4_simple_transmit.c" file. can anyone please help me by sending a link of the examples.(Please visit the site to view this file) (
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Forum Post: TIEVM-VIENNARECT: VIENNA TMSF28379D schematic diagram，the code control loop
Part Number: TIEVM-VIENNARECT I have some question about 28379D controlCARD and TIEVM-VIENNARECT. 1. How did the relationship in the red box come about? 2. What does N mean here?What does this red box represent? 3.What are the control boards corresponding pins for SD_clk and SD_data 1/2/3 ?Is this SDFM module useful in the code you provide，Or standby? 4.F2837x_180controlCARD_R1_3 is the latest schematic diagram?Is there an Altium designer version of the schematic of the control board? can you send me?I bought the board of your VIENNA rectifier and the control board of 28379D.
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Forum Post: RE: CCS/TMS320F28379D: SPACE VECTOR PWM GENERATION USING F28379D
1. Some of the variable names are not logical and leads to this confusion. This is a very old code. You can look at v.FreqMax as the max step angle corresponding to max sine frequency. v.Freq is the frequency of sine wave in normalized for (0 to 1pu). This multiplication helps to get the incremental step angle to step through the sine LUT at this given v.Freq. 2. You will have to figure out a way after better appreciation of how these modules work. 3. I would consider using SVGENDQ
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Forum Post: RE: MSP432P4111: ADC14 consuming unexpectedly large amount of power
I do not see the same current with the attached example. I am also using energy Trace, so it is possible that I am missing the peaks. Regards, Chris(Please visit the site to view this file)
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Forum Post: RE: TMS570LS3137: CDDIS Register settings
Hello, You are right, VCLK4 is not supported on LS3137. Writing 0 and 1 to bit 9 has no effect to clock settings. I will report this to HALCoGen team. Thanks
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Forum Post: RE: TMS320F28379D: Is my hardware capable of reading hall sensors via eCAP
Hi Sven, Your question mentions eCAP and eQEP. Which module did you plan on using to measure the hall sensor?
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Forum Post: RE: TMS320F28069: ADC result differneces by the adjacent pin voltage input
Hi A.Fujinaka, For (1) and (3): Double-sampling A2 on SOC0 then SOC1 also works because the SOC0 sample pre-charges the S+H capacitor to a value near the target value. Note that on this device, since simultaneous sampling is possible, B channels and A channels use separate S+H circuits. This is why even when SOC0 samples B1 as +3.3V, the subsequent sample on A2 is too low, not too high: the +3.3V is not sampled into the same capacitor used to sample the target voltage. For (2): Your understanding is correct: RC has been reduced to the point that op-amp BW becomes the limiting factor, so reducing RC further doesn't help much.
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Forum Post: RE: TMS320F280049: ADC input shows high leakage current about 8uA++
Hi Wilson, Were you able to determine the source of the leakage?
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Forum Post: RE: TM4C123GH6PM： How to make USB Composite devices provide different PID/VID
Hello, Can you send me your project so I can test it on my end? Also just to check, but are you still using the TI VID/PID? Because our descriptors won't work without our VID/PID and if you change that then you would need to register new signed descriptors with Windows.
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Forum Post: RE: CCS/MSP432P401R: Error 1141 - No access to CS_DAP_0. Can't connect to target.
Hello, How is the power being provided to the board? Are you using the 10-pin or 20-pin interface? I have had issues in the past associated with the power and sense lines not being connected correctly on the target board for the XDS200 and the 20-pin interface. REgards, Chris
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Forum Post: TIDM-1019: Calibration Table
Part Number: TIDM-1019 Hi, I've a problem with the adv. calibration Table, when enable, i don't have correct results. I'll explain all the steps i've done so far. I've Flash my card with your default program (clean install), the only change in your code is the following one : alg_results_float.volumeFlowRate *= 10.0; //10x multiply There is the result of our testing bench with adv. calibration table disable : As you can see, the error is "correct" from Q4 (4741.19L/h) to 420.08L/h ( volume error of water going through the water meter). Then I'm doing the calibration with USS (adv. calibration table disable) . I will use 3 ranges Then, I disconnect the card, enable Adv. Calibration Table, generate headers, rebuild the program and flash the card. I connect the card to USS, looking at the waveforms and check Adv. Calibration Table Mean value stay at 0, it's perfect because no water is going through the water meter, but I've the following error : 1 ) I've an error 134 (The minimum volume flow rate falls outside the lowest alpha min calibration point), I guess it's linked to the second problem. How to fix this error ? By editing the "Flow minimum" of the first range ? Which value then ? 2) Volume on the card (LCD) stay at 0 and do not change when water is going through the water meter I do a test at Q1 (26.361 L/h) with Adv. calibration Table disable, seems correct same result for the mean value when i was doing the calibration Then i check Adv. calibration Table Mean value is at 7.29 L/h and really far from Q1 (26.361 L/h), why ? I've the same behavior for other flow rates Best Regards, Maxime
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Forum Post: RE: TMS320F280049: ADC input shows high leakage current about 8uA++
hi Devin, I think we are pretty close to determine the root cause of this substantial voltage drop across the analog inputs. It seems that it got to do with the C2000 ADC setting that sample the analog inputs at 150nsec (sample and hold time). There are a bunch of fast ADC that has 100Ohm and 100pF as the RC to this ADC, these are not having any voltage drop issue. Those that are having 18.7KOhm and 1uF as RC have voltage drop issue. As soon as those big RC reduced to 100Ohm and 100pF, the voltage drops is gone ! I have just tested it on one analog input. Will confirm this further. Thanks for following up! regards Wilson
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Forum Post: RE: TMS320F280049: F280049 oscillator failure when using external crystal
Sounds good Sheldon. Glad they figured out what the issue was.
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Forum Post: RE: RM48L952: RAM ECC single bit error test fails if repeated
Hi QJ Wang, The mechanism you mention "cache is a special buffer designed for ECC", is not documented. Looking into ARM technical reference seems that it is implemented into R7 architecture ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0458c/BGBFGEFD.html ) but not in R4. Is this the one you were referencing? Is it undocumented for R4? How deep is that cache? We really need more details on RAM ECC to face questions and tests with our TUV assessors. RAM ECC is a fundamental safety mechanism. We do not understand its behavior in many circumstances and it is difficult to implement systematic tests in these conditions. For example explain the behavior of the following code, it is executed right at the end of initialization produced by HALcogen "_c_int00()". I just wanted to understand how RAM ECC was changed, but it seems not predictable. Code just changes RAM content and reads corresponding ECC. According to documentation RAM ECC can be read always, even if ECC write is not enabled. Consider "_coreEnableRamEcc_()" has been called before. 3 things are strange (red in code comments) The 8 bytes for a single ECC location are not equal within the same 64 bit (it should according to your documentation) ECC doesn't change anymore after the first write to RAM A data abort is raised if read is performed on a second location and then back on the first location void triggerECCabort() { #define tcramAddress1 (0x08000010U) #define tcram1Location (*(volatile uint64 *)(tcramAddress1)) #define tcram1EccLocation (*(volatile uint32 *)(tcramAddress1|0x0400000U)) #define tcramAddress2 (tcramAddress1+0x10) #define tcram2Location (*(volatile uint64 *)(tcramAddress2)) #define tcram2EccLocation (*(volatile uint32 *)(tcramAddress2|0x0400000U)) volatile SIS_U32 ramEccread = 0U; //DEBUG: All ram is zeroed and ECC memory is all 0x0C /* Location 1: change value in RAM and view corresponding value in ECC RAM */ ramEccread = tcram1EccLocation; //ECC=0x0C0C0C0C tcram1Location = 4U; // write in RAM something ramEccread = tcram1EccLocation; //ECC changes to 0xDFDFDFDB, 1. why least significant byte is read differently? tcram1Location = 312312U; // write in RAM something ramEccread = tcram1EccLocation; // 2. ECC does not change, why ? /* Location 2: change value in RAM and view corresponding value in ECC RAM */ ramEccread = tcram2EccLocation; tcram2Location = 4U; ramEccread = tcram2EccLocation; tcram2Location = 312312U; ramEccread = tcram2EccLocation; /* Again Location 1: change value in RAM and view corresponding value in ECC RAM */ ramEccread = tcram1EccLocation; // 3. This causes a data abort, from Fault Status Registers I see it is from source "Synchronous Parity or ECC Error". Why?? tcram1Location = 4U; ramEccread = tcram1EccLocation; tcram1Location = 312312U; ramEccread = tcram1EccLocation; } Are we missing something? Strangely if I disable ECC (_coreDisableRamEcc_) problems 1 and 2 disappear. Even 3 but I guess due to the missing ecc check. Regards, Valerio
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Forum Post: CCS/MSP432E401Y: Cannot open serial Port XDS110 Class Application/User UART
Part Number: MSP432E401Y Tool/software: Code Composer Studio Hey, for some reason I cannot open the serial port of the Launchpad on my PC. I loaded the uart_echo_MSP_EXP432E401Y_nortos_ccs example and use PuTTY to access the serial Port. On my laptop it is working well, but on my other PC I get following error message from PuTTY: Did I forget do install some drivers? CCS v.9. is there and I can load the uart_echo program to the MSP432 Launchpad from the PC. Thanks for your help! best regards Tiemo
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Forum Post: RE: TMS320F280049: ADC input shows high leakage current about 8uA++
Hi Wilson, Thanks for posting an update. Are you sampling when the measurement is taken? In that case I think the issue is likely the IR drop due to inrush current from sampling. Sampling faster/slower would modulate this drop. Is the measurement taken with the ADC itself, or a DMM? If the ADC itself, the issue may be that the S+H cap can't be charged in time through the large RC. Reducing the RC and/or increasing driver BW and/or increasing S+H duration by increasing ACQPS setting may help. Not sure if large RC explains true pin leakage (measured by a DMM with ADC not sampling), but reducing the R will certainly reduce how much IR drop occurs. Note: if the thread locks but you want to continue the discussion, use the 'Ask a related question' button.
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Forum Post: RE: MSP430FR5994: Suspending LEA operation
Hi Rosh, I will submit the request. In the meantime, can you provide any comments about your use-case for this functionality? Although I understand that it might be useful, we haven't seen cases where this is a critical requirement, especially since the CPU can still run in parallel. Regards, Luis R
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Forum Post: RE: TIEVM-VIENNARECT: VIENNA rectifier communication lights are not bright：A:D3 and A:D4,I dont know if the hardware question or it need configure,can anyone help me?
Hi, I notice you create another thread so I will go ahead to close this one since the problem has been solved. Thanks. Regards, Chen
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Forum Post: TMS320F28069M: F.A.S.T. and Motion support in future chips
Part Number: TMS320F28069M I'm trying to understand your C2000 roadmap as it applies to PM motor control. I have looked at you new series of chips and some have FOC (and F.A.S.T.? cannot tell from description), but none of the new cool chips have Motion support like the TMS320F28069M. Is it available in any of the new chips? If not, will it be available in the future?
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