In the example code you provided above the include appears different. /* DriverLib Includes */ #include I would recommend updating to the latest version of the SDK. Regards, Chris
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Forum Post: RE: CCS/MSP432P401R: MSP432P401R, How to configure SYSTICK
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Forum Post: TMS570LS3137: Driver for connecting S29GL256S10 NOR Flash to TMS570LS3137
Part Number: TMS570LS3137 Hello, I need the NOR flash driver for connecting on EMIF Parallel interface S29GL256S10 (256Mb) NOR Flash to TMS570LS3137 . Thanks,
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Forum Post: RE: CCS/TMS320F28033: C2000 programming issue
Shashwat Tyagi, The memory map in the device datasheet will say what this address location corresponds to. It is an address location in flash sector A: The 'Error -180' before that is point to a power loss issue. Per the wiki below "This error means the JTAG debugger is unable to sense the presence of a power supply voltage on the target". http://software-dl.ti.com/ccs/esd/documents/ccsv7_debugging_jtag_connectivity_issues.html What sort of hardware is the customer using? Is it a custom board? Best, Kevin
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Forum Post: RE: F28M36P63C2: UniFlash programming
Thanks for your assistance... To clarify, you are loading a binary file (.bin) to the M3 core? (versus hex or .out files) Correct. And you are able to load it correctly if you load your baseline binary file, but if you change a byte in your baseline file from 0xE5 to 0x66, it stops loading correctly and instead the flash is empty after loading? Correct. UniFlash says it loaded correctly with no errors yet inspection in memory browser shows its blank and also fails verification. If you are loading binary files, please make sure the start address is the same when you click the 'Load Image' button and when you click the 'Verify Image' button. This ensures that you are loading and verify the same location. I use the same start address as when the baseline was created. I have made the file names the start address for this reason.
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Forum Post: CCS/TMS320F28379D: Serial Flash Programmer Attempting Autobaud to load kernel
Part Number: TMS320F28379D Tool/software: Code Composer Studio Hi, I try to test SCI flash kernel example using serial flash programmer. The program stucks on "attempting autobaud to load kernel" message. I am using controlCARD docking station with F2837x Controlcard. Before running serial flash programmer, I power off device and controlCARD docking station to reset. The blink_dc_cpu01.txt and F2837xD_sci_flash_kernels_cpu02.txt files which are in c2000 serial flash programmer file. What can be problem ? Thanks and regards.
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Forum Post: RE: TMS320F28034: HALT mode
Holger, How frequently does this happen? Is it easily reproducible?
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Forum Post: Compiler/TMS320F28335: Compiler not abiding by __inline and FUNC_ALWAYS_INLINE
Part Number: TMS320F28335 Tool/software: TI C/C++ Compiler Hello, Hello, I created a class for writing and reading to an FPGA. One of the functions is given below, which is contained in a header file with the class declaration. The compiler is not inlining the function. I also tried adding the #pragma FUNC_ALWAYS_INLINE before each of the member function declarations, but that also didn't cause the compiler to inline the functions. What am I doing wrong? Thanks, Stephen #pragma FUNC_ALWAYS_INLINE __inline FPGADATA Fpga::tReadValue(FPGA_ADDRESS tAddress) { FPGADATA tReturnValue; DINT; DRTM; tReturnValue = *(FPGADATA*)(FPGA_BASE_ADDRESS + tAddress); EINT; ERTM; return tReturnValue; }
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Forum Post: MSP430FR5739: MSP430 UART not receiving data
Part Number: MSP430FR5739 Hello, I'm working on a project that will have an MSP430FR5739 incorporated into a device. This is the first time I've worked with a microcontroller, so I'm just trying to figure out how to use each sub-system. I'm trying to figure out how to send UART data to the chip. I have the MSP-EXP430FR5739 Experimenter's Board, and I'm using that to test my code before moving to the real-life device. In order to test the UART, I've got code that looks like the following: #include #include //UART parameters, pulled directly from example code. #define SMCLK_115200 0 #define SMCLK_9600 1 #define ACLK_9600 2 //These are just arbitrary constants for the set_GPIO function. #define Pin_J0 99 #define Pin_J1 98 #define UART_MODE SMCLK_9600 void initGPIO() { PJDIR = 0b00000011; //PJ.1, PJ.0 } void initClockTo16MHz() { // Clock System Setup CSCTL0_H = CSKEY_H; // Unlock CS registers CSCTL1 = 0; // Clear DCO settings CSCTL1 |= DCORSEL | DCOFSEL_2; // Set DCO to 16MHz // Set all clocks to run off the DCO CSCTL2 = SELA__DCOCLK | SELS__DCOCLK | SELM__DCOCLK; CSCTL3 = DIVA_0 | DIVS_0 | DIVM_0; // set all dividers to /1 CSCTL4 |= XT1DRIVE_0; CSCTL4 &= XT1OFF; do { CSCTL5 &= ~XT1OFFG; // Clear XT1 fault flag SFRIFG1 &= ~OFIFG; }while (SFRIFG1&OFIFG); // Test oscillator fault flag CSCTL0_H = 0; // Lock CS registers } void initUART() { // Configure USCI_A0 for UART mode UCA0CTLW0 = UCSWRST; // Put eUSCI in reset #if UART_MODE == SMCLK_115200 UCA0CTLW0 |= UCSSEL__SMCLK; // CLK = SMCLK // Baud Rate Setting // Use Table 30-5 in Family User Guide UCA0BR0 = 8; UCA0BR1 = 0; UCA0MCTLW |= UCOS16 | UCBRF_10 | 0xF700; //0xF700 is UCBRSx = 0xF7 #elif UART_MODE == SMCLK_9600 UCA0CTLW0 |= UCSSEL__SMCLK; // CLK = SMCLK // Baud Rate Setting // Use Table 30-5 in Family User Guide UCA0BR0 = 104; UCA0BR1 = 0; UCA0MCTLW |= UCOS16 | UCBRF_2 | 0xD600; //0xD600 is UCBRSx = 0xD6 #elif UART_MODE == ACLK_9600 UCA0CTLW0 |= UCSSEL__ACLK; // CLK = ACLK // Baud Rate calculation // 32768/(9600) = 3.4133 // Fractional portion = 0.4133 // Use Table 24-5 in Family User Guide UCA0BR0 = 3; // 32768/9600 UCA0BR1 = 0; UCA0MCTLW |= 0x9200; //0x9200 is UCBRSx = 0x92 #else # error "Please specify baud rate to 115200 or 9600" #endif UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI } void set_GPIO(pin, state) { if(pin == Pin_J0) { if (PJOUT & 0b00000001) PJOUT &= (state * 0b00000001); else PJOUT |= (state * 0b00000001); } if(pin == Pin_J1) { if (PJOUT & 0b00000010) PJOUT &= (state * 0b00000010); else PJOUT |= (state * 0b00000010); } } void delay_milliseconds(int duration) { //Each loop here will wait 1 ms (since clock is 16 MHz) until duration is empty. while(duration) { __delay_cycles(16000); duration --; } } //************************************************************* int main(void) { WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer //UART stuff is here initClockTo16MHz(); initUART(); initGPIO(); while(1) { delay_milliseconds(1000); if (UCA0IFG & UCRXIFG) { set_GPIO(Pin_J1,1); delay_milliseconds(1000); set_GPIO(Pin_J1,0); } set_GPIO(Pin_J0,1); delay_milliseconds(1000); set_GPIO(Pin_J0,0); } } I understand that this code could be greatly improved, and I should probably be using interrupts, but right now I just want to get some evidence that my board is receiving UART data. As far as I understand, my code should run, flashing the J0 LED, forever, until it receives UART data. Once it receives data, the UCRXIFG flag should activate and therefore UCA0IFG & UCRXIFG should return "true", and it should flash the J1 LED once. When I send data from a terminal on my computer (using the Serial Monitor in the Arduino IDE, with baud rate set to 9600), I don't get the second blinking LED. I have attached an oscilloscope to the RXD line to confirm data being sent. With the oscilloscope connected, I punched an R into the Serial Monitor on my computer. I measured a waveform that went (Where H is high and L is low): HHHHHHHHHHHHHHHLLHLLHLHLHLLHLHLLLLHHHHHHHHHHHH. I picked apart this data using an ASCII table, and it shows a start bit, an R, a stop bit, a start bit, a NL line feed, and a final stop bit (which blends into the signal going back to its resting high state). So the correct data is definitely getting sent along to the board. I have all the jumpers set up on the board so that they're arranged the way it came, with the jumpers all lined up to jump across the dotted line on the board. So if I have verified that the right data exists on the board, why am I not seeing my code flash the J1 LED, given that sending an R should result in the UCRXIFG flag being set? I think I did everything right in my UART setup to end up with a 9600 baud rate, one stop bit, and no parity, but maybe there's something else I'm missing? Unfortunately all the example code in the Resource Explorer uses interrupts, which I'm not looking to do yet. Again, just trying to start getting my feet wet with simple, linear-executing programming before I then move on to handling interrupts and how those work. Thanks!
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Forum Post: CCS/TMS320F28035: cannot connect the debugger
Part Number: TMS320F28035 Tool/software: Code Composer Studio Team, My customer is using TMS320F28035 device on his board, and cannot connect the debugger. Details: I tried two XDS200 and XDS510 both cannot connect. My CCS is in 7.2.0.00013 version. This is the error message from XDS510: And XDS200: I checked the crystal oscillator signal at X2 and it seems to be good: The same with power supply I have very stable 3.34V and 1.9V. I have my suspicious on the reset signal XRS. I have it pulled up by 10k resistor to 3.3V with 1nF capacitor so it should be at high state but I see some internal resets on the XRS by the micro. It is at about 74kHz frequency with duration about 50us see below this is the power up XRS signal: Why I see the internal reset any idea? I use the DSP2803x_CSMPasswords.asm routine but with password set to all FFFFs. Is it possible that during the internal resets on XRS the erasing crushed and wrote some random number or zeros locking the device? The JTAG signals seems to be good as well I am getting the clock and TRST signal is going up when trying to connect. JTAG clock TCK 12MHz (XDS510 usb): I would really apricate your quick help with my issue. P.S. I use 7.2 CCS due to some problems with installation of any newer version. I think my corporate computer setting does not let for installing the new Code Composers. The 7.2 or order are the only version I can install the newer ones are not possible to install. Thanks Viktorija
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Forum Post: TMS570LS3137: Performance Monitor: How to set Cortex-R4F PMCNTENSET.C (Cycle counter enable bit)
Part Number: TMS570LS3137 Hi there, I'm trying to use the PMU by including HalCoGen 04.06.00 generated sys_pmu.asm and sys_pmu.h in my project. My code structure is in the form of: _pmuInit_(); _pmuEnableCountersGlobal_(); _pmuSetCountEvent_(0, 0); while (TRUE) // embedded software: endless loop { _pmuResetCycleCounter_(); _pmuStartCounters_(0x1); [Some code here ...] _pmuStopCounters_(0x1); int count=_pmuGetCycleCount_(); [More code here ...] } } However, the PMCNTENSET.C bit (cycle count enable) remains disabled all the time so the counter is not counting. If I enable this bit using the debugger, everything seems fine. Did I forget to call another function to enable that bit, or, are my arguments to the called function wrong? Thank you!
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Forum Post: TMS320F280049: how to understand the timing parameters for TMU
Part Number: TMS320F280049 As indicated in table 2-1 in the TRM, operation a=b/c needs 5 pipeline cycles. Could you help explain how long it takes? I am not so clear about the relationship between pipeline cycle and CPU cycle. Thank you.
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Forum Post: TMS320F280049: Is there the RAM initialization process after XRS reset?
Part Number: TMS320F280049 As indicated in the Table 4-10 Boot ROM Reset Causes and Actions in F28004X TRM, XRS reset will bring with the below process. I want to confirm whether the RAM initialization will occur after XRS reset. Customer wants to keep the content in some parts of RAM after the XRS reset. 1. Adjust clock divider to /1 2. Device configuration 3. Clear boot stack 4. Continue default boot flow
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Forum Post: TMS570LS1227: Re-read the slave while the slave respond NAK for it need more time to process the request
Part Number: TMS570LS1227 Hi, I have TMS570LS1227 HDK that i am using with the I2C slave chip. The master i2c configuration is as below. /** - set i2c mode */ i2cREG1->MDR = (uint32)((uint32)0U EMDR = 0U; /** - Disable DMA */ i2cREG1->DMACR = 0x00U; /** - set i2c data count */ i2cREG1->CNT = 8U; /** - disable all interrupts */ i2cREG1->IMR = 0x00U; /** - set prescale */ i2cREG1->PSC = 10U; /** - set clock rate */ i2cREG1->CKH = 36U; i2cREG1->CKL = 36U; /** - set i2c pins functional mode */ i2cREG1->PFNC = (1U); /** - set i2c pins default output value */ i2cREG1->DOUT = (uint32)((uint32)1U DIR = (uint32)((uint32)1U PDR = (uint32)((uint32)1U PDIS = (uint32)((uint32)0U PSEL = (uint32)((uint32)1U NAK, 0xFF +ACK...until it will respond with ACK for the read. Time [s] Analyzer Name Decoded Protocol Result 0.24614475 I2C Setup Read to [0xC9] + ACK 0.246235625 I2C 0x04 + ACK 0.246334 I2C 0x11 + ACK 0.24643725 I2C 0x33 + ACK 0.246543 I2C 0x43 + NAK 0.250027375 I2C Setup Write to [0xC8] + ACK 1st write to request slave 0.25011825 I2C 0x03 + ACK 0.2502115 I2C 0x27 + ACK 0.25030475 I2C 0x81 + ACK 0.250400625 I2C 0x04 + ACK 0.250498875 I2C 0x00 + ACK 0.25059975 I2C 0x00 + ACK 0.250698 I2C 0x8E + ACK 0.250796375 I2C 0x54 + ACK 0.250892125 I2C 0x00 + ACK 0.250990375 I2C 0x00 + ACK 0.25108875 I2C 0x00 + ACK 0.2511845 I2C 0x00 + ACK 0.251282875 I2C 0x00 + ACK 0.25138125 I2C 0x00 + ACK 0.251477 I2C 0x0E + ACK 0.25157775 I2C 0x54 + ACK 0.251676125 I2C 0x00 + ACK 0.251774375 I2C 0x00 + ACK 0.25187025 I2C 0x00 + ACK 0.2519685 I2C 0x00 + ACK 0.25206675 I2C 0x00 + ACK 0.252162625 I2C 0x00 + ACK 0.252260875 I2C 0x0E + ACK 0.252359125 I2C 0x54 + ACK 0.252455 I2C 0x00 + ACK 0.25255325 I2C 0x00 + ACK 0.252654 I2C 0x00 + ACK 0.252752375 I2C 0x00 + ACK 0.25284825 I2C 0x00 + ACK 0.2529465 I2C 0x00 + ACK 0.25304475 I2C 0x0E + ACK 0.253140625 I2C 0x54 + ACK 0.253238875 I2C 0x00 + ACK 0.25333725 I2C 0x00 + ACK 0.253433 I2C 0x00 + ACK 0.253531375 I2C 0x00 + ACK 0.253632125 I2C 0x00 + ACK 0.2537305 I2C 0x00 + ACK 0.25382875 I2C 0x46 + ACK 0.253924625 I2C 0x64 + ACK 0.2540505 I2C Setup Read to [0xC9] + NAK 1st Read to slave for the result 0.25414125 I2C 0xFF + ACK 0.25725775 I2C Setup Read to [0xC9] + NAK 0.2573485 I2C 0xFF + ACK 0.26026525 I2C Setup Read to [0xC9] + NAK 0.260356 I2C 0xFF + ACK 0.2632345 I2C Setup Read to [0xC9] + NAK 0.26332525 I2C 0xFF + ACK 0.266262625 I2C Setup Read to [0xC9] + NAK 0.2663535 I2C 0xFF + ACK 0.269270125 I2C Setup Read to [0xC9] + NAK 0.269361 I2C 0xFF + ACK 0.272236375 I2C Setup Read to [0xC9] + NAK 0.272327125 I2C 0xFF + ACK 0.275285125 I2C Setup Read to [0xC9] + NAK 0.275376 I2C 0xFF + ACK 0.278275125 I2C Setup Read to [0xC9] + NAK 0.278365875 I2C 0xFF + ACK 0.281220625 I2C Setup Read to [0xC9] + NAK 0.281311375 I2C 0xFF + ACK 0.28424875 I2C Setup Read to [0xC9] + NAK 0.2843395 I2C 0xFF + ACK 0.28725625 I2C Setup Read to [0xC9] + ACK Slave respond successfully 0.287347125 I2C 0x04 + ACK 0.2878655 I2C 0x00 + ACK 0.287966375 I2C 0x03 + ACK 0.28807225 I2C 0x40 + NAK 0.289808625 I2C Setup Write to [0xC8] + ACK 2nd Write to request slave 0.289899375 I2C 0x03 + ACK 0.289992625 I2C 0x27 + ACK 0.290091 I2C 0x81 + ACK 0.29018675 I2C 0x00 + ACK 0.290285 I2C 0x00 + ACK 0.29038325 I2C 0x01 + ACK 0.290479125 I2C 0x04 + ACK 0.290577375 I2C 0x05 + ACK 0.290675625 I2C 0x05 + ACK 0.290771375 I2C 0x05 + ACK 0.29087225 I2C 0x11 + ACK 0.2909705 I2C 0x22 + ACK 0.291068875 I2C 0x33 + ACK 0.291164625 I2C 0x44 + ACK 0.291262875 I2C 0x00 + ACK 0.29136125 I2C 0x00 + ACK 0.291457 I2C 0x00 + ACK 0.29155525 I2C 0x00 + ACK 0.291653625 I2C 0x00 + ACK 0.2917495 I2C 0x00 + ACK 0.29185275 I2C 0x00 + ACK 0.2919485 I2C 0x00 + ACK 0.292046875 I2C 0x00 + ACK 0.29214275 I2C 0x00 + ACK 0.292241 I2C 0x00 + ACK 0.29233925 I2C 0x00 + ACK 0.292435125 I2C 0x00 + ACK 0.292533375 I2C 0x00 + ACK 0.29263175 I2C 0x00 + ACK 0.2927275 I2C 0x00 + ACK 0.29283075 I2C 0x00 + ACK 0.292929125 I2C 0x00 + ACK 0.2930275 I2C 0x00 + ACK 0.29312575 I2C 0x00 + ACK 0.2932215 I2C 0x00 + ACK 0.293319875 I2C 0x00 + ACK 0.29341825 I2C 0x00 + ACK 0.293514 I2C 0x00 + ACK 0.29361225 I2C 0x02 + ACK 0.2937105 I2C 0x3B + ACK 0.2938365 I2C Setup Read to [0xC9] + NAK 2nd read to slave results 0.29392725 I2C 0xFF + ACK 0.297190875 I2C Setup Read to [0xC9] + NAK 0.29728175 I2C 0xFF + ACK 0.300219125 I2C Setup Read to [0xC9] + NAK 0.300309875 I2C 0xFF + ACK 0.303226625 I2C Setup Read to [0xC9] + NAK 0.303317375 I2C 0xFF + ACK 0.306213375 I2C Setup Read to [0xC9] + NAK 0.30630425 I2C 0xFF + ACK 0.309162 I2C Setup Read to [0xC9] + NAK 0.30925275 I2C 0xFF + ACK 0.3121695 I2C Setup Read to [0xC9] + NAK 0.31226025 I2C 0xFF + ACK 0.315363 I2C Setup Read to [0xC9] + NAK 0.315453875 I2C 0xFF + ACK 0.31913925 I2C Setup Read to [0xC9] + NAK 0.31923 I2C 0xFF + ACK 0.32214675 I2C Setup Read to [0xC9] + NAK 0.3222375 I2C 0xFF + ACK 0.32509525 I2C Setup Read to [0xC9] + NAK 0.325186 I2C 0xFF + ACK 0.32816475 I2C Setup Read to [0xC9] + ACK successful slave result 0.328255625 I2C 0x04 + ACK 0.328811625 I2C 0x00 + ACK 0.328912375 I2C 0x03 + ACK 0.32902075 I2C 0x40 + NAK 0.3336655 I2C Setup Write to [0xC8] + ACK 0.33375625 I2C 0x03 + ACK 0.333849625 I2C 0x0B + ACK 0.333942875 I2C 0x82 + ACK 0.334043625 I2C 0x00 + ACK 0.3341395 I2C 0x00 + ACK 0.33423775 I2C 0x00 + ACK 0.334336 I2C 0x11 + ACK 0.334431875 I2C 0x22 + ACK 0.334530125 I2C 0x33 + ACK 0.334628375 I2C 0x44 + ACK 0.33472425 I2C 0x3E + ACK 0.3348225 I2C 0xD2 + ACK 0.334948375 I2C Setup Read to [0xC9] + NAK 0.335039125 I2C 0xFF + ACK 0.338117375 I2C Setup Read to [0xC9] + NAK 0.33820825 I2C 0xFF + ACK 0.341062875 I2C Setup Read to [0xC9] + NAK 0.34115375 I2C 0xFF + ACK 0.344049 I2C Setup Read to [0xC9] + NAK 0.344139875 I2C 0xFF + ACK 0.3470565 I2C Setup Read to [0xC9] + NAK 0.347147375 I2C 0xFF + ACK 0.350398625 I2C Setup Read to [0xC9] + NAK 0.350489375 I2C 0xFF + ACK 0.353406125 I2C Setup Read to [0xC9] + NAK 0.353496875 I2C 0xFF + ACK 0.35649625 I2C Setup Read to [0xC9] + NAK 0.356587125 I2C 0xFF + ACK 0.359589625 I2C Setup Read to [0xC9] + NAK 0.359680375 I2C 0xFF + ACK 0.362535125 I2C Setup Read to [0xC9] + NAK 0.362625875 I2C 0xFF + ACK 0.36610075 I2C Setup Read to [0xC9] + NAK 0.3661915 I2C 0xFF + ACK 0.36919475 I2C Setup Read to [0xC9] + NAK 0.3692855 I2C 0xFF + ACK 0.372450375 I2C Setup Read to [0xC9] + NAK 0.372541125 I2C 0xFF + ACK 0.37531625 I2C Setup Read to [0xC9] + NAK 0.375407 I2C 0xFF + ACK 0.378344375 I2C Setup Read to [0xC9] + NAK 0.378435125 I2C 0xFF + ACK 0.3812485 I2C Setup Read to [0xC9] + NAK 0.38133925 I2C 0xFF + ACK 0.384442125 I2C Setup Read to [0xC9] + NAK 0.384532875 I2C 0xFF + ACK 0.387490875 I2C Setup Read to [0xC9] + NAK 0.38758175 I2C 0xFF + ACK 0.390460125 I2C Setup Read to [0xC9] + NAK 0.390551 I2C 0xFF + ACK 0.393736375 I2C Setup Read to [0xC9] + NAK 0.393827125 I2C 0xFF + ACK 0.39659925 I2C Setup Read to [0xC9] + NAK 0.39669 I2C 0xFF + ACK 0.39966875 I2C Setup Read to [0xC9] + ACK successful result 0.399759625 I2C 0x04 + ACK 0.4003205 I2C 0x00 + ACK 0.400421375 I2C 0x03 + ACK 0.400524625 I2C 0x40 + NAK If i try to implement this in TMS570LS12x, the master pull down the SCL line as soon as the slave responds NAK for the read. setting the ignore NACK in EMDR doesnt help as it just continue read and copy the data as 0xFF for 4 times as the counts set to 4. In the above picture once the slave respond NAK for the read and 0xFF+ACK, the SCL is held for ~3millisec and re read the slave and continues... How do we recover the TMS570LS12x master once it stuck with NAK response from slave and to implement the above fucntions? Could you please help me to implement this in TMS570LS12x controller? Thanks, Best Regards, -Dinesh
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Forum Post: TIDM-DELFINO-ETHERCAT: TMS320F2837xD MCUs
Part Number: TIDM-DELFINO-ETHERCAT Hi, Is it possible to implement Model predictive controller (MPC) algorithm on Delfino Lauchpad?. If someone already did so, please let me know. Regards, Satheesh
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Forum Post: TMS320F280041: Question on prevent an ADC interrupt overflow
Part Number: TMS320F280041 Hi Vivek, I'd like to ask some question based on this thread: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/750511?TMS320F280041-F280041-ADC-Interrupt-Overflow-Issue#pi320995=1 Regarding your reply to Ricky, you suggest us to clear INT1E before clear ADC interrupt and ADC INT overflow flag, after that set this bit to high. Could you help me understanding the reason behind? It do works but I think in this circumstance not ADC INT overflow flag will be set. Is my understanding right? My customer meet the same problem and would like to know the mechanism. Thanks!
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Forum Post: TMS320F28069M: unrolling stack trace on watchdog reset
Part Number: TMS320F28069M when the watchdog is setup for automatic reset, is there any way to breakpoint it before the reset occurs? Got a rare-and-random reset occuring in the software: it'd be good to identify any watchdog timeouts and unroll the call stack to identify whats going wrong.
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Forum Post: MSP430FR5972: MSP430FR5972
Part Number: MSP430FR5972 I realise most will think this an odd question, but can anyone show me skeleton State Machine code in Assembler? Many decades ago I designed a telephone answering machine using an 8051 using a State Machine to control everything. It was messy crossing page boundaries (an 8-bit machine) and I think it should be easier using an MSP430. But, since I got a complete remote controlled, voice synthesis answering machine in 1kB of code (8048 version of 8051), using Assembler, I would like to try to see how compact an MSP430 Assembler State Machine could be. The State Machine comprised nested Master and Sub States and was extremely simple to change and fault-find since all functions could be isolated and tested separately. Unfortunately, there is a dearth of information on Assembly programming for the MSP430s so if anyone could help, I would appreciate it - mainly, I guess, how do I do conditional Jumps, and are there page limitations on how far I can Jump? Cheers - John
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Forum Post: MSP430FR5964: FRAM erased after power cycle
Part Number: MSP430FR5964 All of main FRAM except for information memory is erased when the device is power cycled. We've tried completely disabling the BSL, with no luck. At power up if the reset is held low while the main 3.3V rail comes up, then memory persists without issues. The scope measurements of the power rails look clean. I was able to reproduce the failure on two boards and believe it might be related to the MSP getting into a weird power state. We have off board inputs that aren't tied to the same power rail as the MSP. If the MSP is power cycled while P3.6 is held high, memory is erased, same isn't true if P3.7 is held high. We're able to reprogram the MSP and it resumes normal functions. I'm having trouble understanding how power sequencing can erase NVM. Any help or further things to test would be appreciated.
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Forum Post: RTOS/MSP432E401Y: BIOS_start query
Part Number: MSP432E401Y Tool/software: TI-RTOS Hello I am using MSP432E401Y development board. In the timerled example, RTOS is used and I observed that if we write any kind of code after BIOS_start(), that part of the code will not work, so why the return is used after BIOS_start(). Please give your suggestion. Thank you
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Forum Post: TMS320F28377D: Boot from SPI with DCSM enabled?
Part Number: TMS320F28377D Hi, I have a bootloader that resides in an EEPROM that can be run from both CPU's. It successfully boots from SPI at powerup and I can use it to download an image to Flash and run it so the boot pins and boot mode seem to be working fine for both CPU's. However, after programming the Z1 CSM password (regs 2 and 3, not ECSL at 0 and 1) and the GRABRAM and GRABSECT to set all flash sectors and RAM to Zone 1 it will not boot from EEPROM. Using a scope, it looks like it's in a loop of trying to read from the EEPROM as there are constant bursts of clock pulses on the pin. Does this have to do with being unable to copy data into secure RAM from outside of the processor? Is it possible to load code from an EEPROM on a locked device or should we move the bootloader from EEPROM to flash? Let me know if something is unclear or if I should add more information. Thanks, - Taylor
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