Part Number: TMS320F28379D Good Afternoon, I wonder if anyone can tell me how fast I can drive the SD filters at a 12 bit effective resolution. We are planning to PWM at 40KHz or faster and to use shunt resistors for current measurement. Thanks, Imre Kiss
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Forum Post: TMS320F28379D: SD filter update rate
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Forum Post: RE: TM4C1233H6PZ: USB interface lacks USB_VBUS signal
Hello Dan, VBUS would not be connected to this device. It would have to be a self-powered USB device. The TM4C1233H6PZ can only be used as a USB Device. As long as you properly configure it as a USB Device in TivaWare, all configurations will be handled. You cannot configure it as a USB Host or USB OTG - if you try to do this, the driver would not work properly as it would try and operate in a mode the device can't support so you'd get errors etc.
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Forum Post: RE: MSP430F5438: BSL Scripter with MSP430F5438 + MSP-FET
Hi Nicholas, Can you try explicitly setting the UART buad rate to 9600? This is not a protected command, so you should be able to do this without a password. Also, can you double check that these other UART parameters are met? Thanks, Mitch
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Forum Post: RE: TM4C123GH6PM: TM4C123GH6PM:
Hi, We provide TivaWare, a library of drivers for your development. Any reason why you want to use any custom driver. Before you update the ICDI firmware as shown below, please try two things. 1. Can you connect to another PC and confirm that all PCs you have will not show the ICDI in the device manager. 2. If you have another LaunchPad, does it get recognized by any of your PCs. The above two experiments is to isolate the problem so we know if the problem is on the PC side or only the problem LaunchPad. If you are successfully to update the ICDI firmware, then try to unlock the device again.
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Forum Post: RE: TIDM-DELFINO-ETHERCAT: problem in the statemachine switch
Hello If there is something specific to the setup of using the C2000 device I can help, but for EtherCAT issues, like this, please post the to the ETG forums: www.ethercat.org Best regards Chris
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Forum Post: RE: TMS570LC4357: FreeRTOS demo hang
Is there a way to recover the stack?
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Forum Post: RE: CCS/TMS320F28335: apply window and fir filter for ADC result
Da, You bring up a good point. ControlSUITE does this extra alignment relative to what is mentioned in the user guide, however C2000Ware v1.00.06.00 does not do the alignment at all (!), if you look at the 2837x_FIR project. I am trying to get an answer to this question internally, and will let you know what I find. In the meantime, on your side, perhaps you could try a few things - like removing the alignment on the FIR object, input and output buffers, and seeing the behavior. If that works, you can take it a step further and remove alignment on the coeffs and delay buffers as well and try and see if that works reliably. My belief is that in general, the alignment is required for performance considerations. Also, I believe 511 is too large and you are running out of RAM hence the linker is generating errors. Could you try with the default number of taps in the example project first? Thanks, Sira
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Forum Post: RE: CCS/TMS320F28335: invalid redeclaration error
Thanks, awaiting updates.
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Forum Post: RE: MSP430F6736A: voltage at RST pin less than AVCC
Hello Moshe, 1. Good point about the internal default pull-up on reset. I had forgotten about this feature on most F5xx and F6xx devices. This means that an external pull-up is not required, but it might still be recommended in this case. 2. Every GPIO will have a very small amount of leakage current, but I don't really think that would be enough to cause the issue here. Is it possible that you are seeing an RC Ripple/averaging effect on the RST line? The fact that you see the voltage rise when you add a 2nd resistor pull-up, basically cutting the pull-up R value in half since it's in parrallel with the internal pull up. This is going to reduce the RC time constant on the RST pin, which will probably increase the voltage but show the noise a bit more. To test this, you could put a cap 1/2 the size instead of the external pull-up and see what kind of effect you see. Thanks, JD
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Forum Post: RE: CC430F5137: Flash Memory is unintentionally rewritten to All F
Hello Katsu, Were you able to solve this issue for the customer? Thanks, JD
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Forum Post: RE: TMS320F28379S: Change SCIBOOT mode to use alternate IO
Hi Andy, Thanks! Ok you may consider the following ideas. 1. Configure the target for SCI boot 2. Program the application into Flash via SCI 3. Once the programming is done, launch the application by jumping into the entry point of the application in Flash. You may consider developing a simple monitor program that asks a few simple questions. Upon startup, the monitor waits for a pre-determined period of time (say 5 secs) for user input to see if there is a request for an application update to be made in Flash. If yes, the Flash update is started and the application is launched. If the answer is “no” or there is no response, the monitor simply launches an existing application If there is one programmed in Flash. If there is no application in Flash, it continues to wait in the monitor. This is a very simple monitor performing a very simple task. You may consider additional ideas for your design. For example, the 5 second startup latency may not be acceptable for your system. In this case, once the application is programmed into Flash, you simply launch the application immediately on startup. If this option is chosen, then how do you update Flash at a later date? To address future updates, the application will need to support accepting a user command by some means to return to the monitor because there is a pending flash update. Also keep in mind that when programming Flash, you must design the methodology in such a manner that you never “brick” :-) the target/product. This means, an error in doing the flash update should not cause a permanent failure in your target/product. You should always be able to recover. So let us define the potential problem a bit. Let us say that your application cannot afford the 5 sec delay In startup and you decide that the monitor will immediately launch the application upon startup. You design in the necessary hooks into the application so it knows how to return to the monitor for a Potential flash update in the future. Sometime in the future you use this approach and do a flash update. Except this time, there is some sort of a problem during the programming ( a power glitch or whatever), And the flash update fails during the course of the update. The programming stops and you think it is done with the update. You power cycle the target, the application is immediately launched but gets lost part way through execution. You cannot command the application to return to the monitor because the app is no longer working as designed. I will leave it to you to think about ways on how to recover from this type of a problem. I hope this feedback is adequate to stimulate thought on how to go about with the design of your system. Please do not hesitate to ask if you need further assistance. Cheers! Krishna
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Forum Post: RE: CCS/TMS320F28377S: 2P 2Z Controller
Naveen, I'm sorry for the delay in responding. I have nothing further to suggest from my side. I have asked some colleagues to look at it but didn't get any feedback so far. I'll post here if they come back to me. Otherwise I regret I don't know. Regards, Richard
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Forum Post: RE: LAUNCHXL-F28069M: c2000 + TMC4671-EVAL+ TMC-UPS-10A70V-EVAL
We have NOT tried that, but may be possible. It is left for the user to figure out such details.
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Forum Post: RE: MSP430F6638: USB BSL Issues
Hello Fusillade, When you perform the initial BSL programming, are the devices blank?
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Forum Post: RE: TMS320F28069: ADC Drop Out
(Please visit the site to view this file)(Please visit the site to view this file)Hi Kevin, Please see below for answers to the questions you need to know more about. 1. Could you compare the actual ADC results (ADCRESULTx register) in a good vs. bad case and provide them? This would be instead of looking at the current measurements recorded, which is calculated based on the read ADC values. The customer is working on finding a way to collect raw ADC through CCS, is this possible? If so, how? Also additional data was collected last night using scope to show measured ADC voltage reading @ ADC micro pin matching measured AC current, but reported reading by micro was incorrect (stopped updating). Phase C where is most susceptible is connected to ADCINA6 thought might indicate something to be last in the ADC queue. 2. Could you provide the ADC initialization code being used? Attached is source code for the ADC functions (including initialization). These were created by TI to their understanding and the customer did not modify them (they are from 2015), so not sure if they contain the errata fixes. 3. As mentioned, there are several ADC advisories in the device errata. Have these been understood and have the suggested workarounds been properly implemented? Currently, they are working through the ADC advisories, and have completed: Initial conversion, ADC result conversion when sampling ends on 14th cycle, ADC revision register limitation ADC can become non-responsive when ADCNONOVERLAP or RESET is called They are still working on the others, and would be happy to review them with us to make sure we implemented them correctly. 4. Could you provide more details on when this issue seems to happen? Is there something in the application that is systematically triggering the ADC results to be bad? Does it appear to happen after a certain length of operation, i.e. what is meant by eventually? Any details you can provide around these occurrences would be helpful in diagnosing the issue. The issue seems to happen after a low power sleep mode is induced and then the controller is woken back up. It is very repeatable on the motor dyne, issue happens after 30 sleep cycles. On the actual project it seems more random. Thanks, Barend
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Forum Post: RE: MSP430F5438: BSL Scripter with MSP430F5438 + MSP-FET
[quote user="Mitch Ridgeway"] Can you try explicitly setting the UART buad rate to 9600? This is not a protected command, so you should be able to do this without a password. Also, can you double check that these other UART parameters are met? [/quote] Hello Mitch, When explicitly setting the UART baud rate to 9600, I receive the same results. I have also tried changing to system to PARITY mode in which there was also no changes. Thank you, Nick
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Forum Post: RE: TMS570LS3137: Linker command file for RAM execution
Hello Steven, You can copy some objects to SRAM and execute the code from SRAM: 1. To create an output section named test1 which is composed of the input sections inside {... ... }. The test1 is allocated to FLASH0 for loading, and allocated to SRAM0 for running. When the program is loaded, test1 is in the FLASH0 memory range. During running sys_startup.c which runs in FLASH0, it copies output section test1 from FLASH0 to SRAM. Note this copy is not done automatically. 1. allocate the output sections (test1) to flash and SRAM /*----------------------------------------------------------------------------*/ /* Section Configuration */ SECTIONS { .intvecs : {} > VECTORS test1: { sys_main.obj (.text) sys_selftest.obj (.text) sys_vim.obj (.text) system.obj (.text) pinmux.obj (.text) esm.obj (.text) rti.obj (.text) errata_SSWF021_45.obj (.text) gio.obj (.text) sys_core.obj (.text) sys_pmu.obj (.text) notification.obj (.text) } load = FLASH0, run = RAM, LOAD_START(loadStart), RUN_START(runStart), SIZE(codeSize) .text : {} > FLASH0 .const : {} > FLASH0 .cinit : {} > FLASH0 .pinit : {} > FLASH0 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM /* USER CODE BEGIN (4) */ /* USER CODE END */ } 2. Copy the output section test1 to SRAM using _copyAPI2RAM_() 3. Please find the code of _copyAPI2RAM_() in TI CAN bootloader
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Forum Post: RE: TMS570LS3137: Linker command file for RAM execution
BTW, you can't execute all the code (for example sys_intvecs.asm) in SRAM.
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Forum Post: LAUNCHXL-F28379D: Dual Core PWM Trip
Part Number: LAUNCHXL-F28379D Hello, My goal is to be able to force the output of all of the PWMs to a low state from either core. For one core, that involves using a GPIO pin connected to the PWM through XBAR Input 1 to the one shot trip zone of the PWMs. This works well, and it can be found in the trip zone example code. However, I'm not sure of a way to be able to trigger the PWMs from either core. The currently unsuccessful method I'm using is to initialize the XBAR and PWM trigger on CPU1. CPU2 is given control of a GPIO pin. If CPU2 needs to trip the PWMs, it would directly control the XBAR connected GPIO. If CPU1 needs to trip the PWMs, it is configured to raise an IPC flag that causes CPU2 to interrupt and directly control the XBAR connected GPIO. Here's the main() code for CPU1 to initialize the PWMs, XBAR, and trigger: EALLOW; GPIO_setPadConfig(32, GPIO_PIN_TYPE_STD); GPIO_setDirectionMode(32, GPIO_DIR_MODE_OUT); GPIO_setMasterCore(32, GPIO_CORE_CPU2); InputXbarRegs.INPUT1SELECT = 32; EPwm1Regs.TZSEL.bit.OSHT1 = 1; EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm2Regs.TZSEL.bit.OSHT1 = 1; EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm3Regs.TZSEL.bit.OSHT1 = 1; EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EDIS; CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; InitEPwmGpio(); EALLOW; EPwm1Regs.TZCLR.bit.OST = 1; EPwm1Regs.TZCLR.bit.INT = 1; EPwm2Regs.TZCLR.bit.OST = 1; EPwm2Regs.TZCLR.bit.INT = 1; EPwm3Regs.TZCLR.bit.OST = 1; EPwm3Regs.TZCLR.bit.INT = 1; EDIS; This code is in an 8kHz timer interrupt on CPU1 used to request a trigger from CPU2 after 4 seconds: static int debugCount = 0; debugCount++; if (debugCount >= 32000) { HWREG(IPC_BASE + IPC_O_SET) = 1UL << IPC_TRIGGER_FAULT; } The following is in main() on CPU2 to initialize the IPC interrupt: EALLOW; PieVectTable.IPC0_INT = &FaultTrigger; EDIS; // Enable CPU INT1 which is connected to Upper PIE IPC INT0-3: IER |= M_INT1; // Enable CPU01 to CPU02 INTn in the PIE: Group 11 interrupts PieCtrlRegs.PIEIER1.bit.INTx13 = 1; // CPU1 to CPU2 INT0 Finally, this is the IPC ISR: __interrupt void FaultTrigger(void) { EALLOW; GpioDataRegs.GPBCLEAR.bit.GPIO32 = 1; // Used to trip the trigger GpioDataRegs.GPBSET.bit.GPIO32 = 1; EDIS; // Clear the IPC flag HWREG(IPC_BASE + IPC_O_CLR) = 1UL << IPC_TRIGGER_FAULT; // Acknowledge IPC INT0 Flag and PIE to receive more interrupts IpcRegs.IPCACK.bit.IPC0 = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; } Is there a simpler approach to this that allows both cores to directly cause the PWM, which is set up on CPU1, to force all of the outputs low? Thanks!
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Forum Post: TMS320F28335: TMS320F28335PTPQ can support PPAP?
Part Number: TMS320F28335 There is AEC-Q100 qualification in datasheet. TMS320F28335PTPQ can support PPAP?
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