Part Number: DRV8301-69M-KIT Hi, I damaged the DRV8301 IC in field weakening zone. I am running the controller with a battery. While testing in field weakening, the BMS cut-off the battery due to some fault and that led to probable overvoltage due to high back-emf and the driver ic got damaged (FETs are still good). I could not capture the waveform though. I am worried if I need to add any protection circuit. I have read many papers on it and here are a few possibilities: 1. Turn all the lower FETs on and that will short circuit the back-emf. a. Since the current would only be limited by motor resistance, will the motor come to a stop all of a sudden? I cannot allow that on my bike. b. Also, my motor resistance is very less - 10mohms. In that case, the current will be very high and it may even damage the FETs? What care I should take? 2. Add a resistor to discharge the DC-Link Cap in case of overvoltage condition. However, I do not prefer this method and I am looking for a better option. 3. In case of fault on BMS side, turn off only the discharge path and keep the charge path on. In that case, the current will continue to go to the battery and save the voltage. But this may possibly damage the batteries if they are already fully charged. Is there any other method? I would like to know your comments on the above points in case if I am wrong or missing something.
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Forum Post: DRV8301-69M-KIT: Damage due to overvoltage
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Forum Post: RE: TMS320F28035: Generating relocatable object file
did you try making the alignment changes in linker command file ? Regards baskaran
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Forum Post: RE: MSP430F5438A: Long delay after SPI byte was shifted out
Hi, 1. Besides, Out of LPM0 will also take some time, about 3us. 2. I advice you to remove LPM0 function and enhance the frequency of MCLK. Then test the delay time. Eason
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Forum Post: RE: TMS320F280049: ROM code
the should have same ROM code if the silicon revisions are same. Regards baskaran
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Forum Post: RE: Compiler/MSP430FR6989: Flashing code onto device using MSPFlasher_1.3.18
Hi, What's the your programmer tool and FR6989 borad? Please try updating the on-board eZ-FET using a different software tool, CCS or FET-Pro430 are recommended. I would also recommend trying a Windows device to update the eZ-FET to see if the issue resides with the Linux drivers. If the eZ-FET is truly bricked then it can only be fixed by connecting a different FET tool to the J101 test points and re-programming the F5528. B.R Winter
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Forum Post: RE: MSP430FR2433: Lowest current that EnergyTrace will show, e.g. of LPM4.5
Hi, Do you have a multimeter with a nA setting? Yes, the lowest current that the multimeter can measure is 10nA. You know goods in China is much cheaper. MSP-EXP430FR6989 LaunchPad is a good choice. Energytrace ++ will communicate with MSP430 and know its state. Since you have find the reason, I will close this post. Eason
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Forum Post: RE: MSP430F5324：MSP430 CLI programmer write direct memory address
Hi zrno soli, I programmer main code before. Base on your suggestion, we create mod_addr.txt file to programmer memory range 0x4400. The screen show as below. As below screen show are before & after memory comparison. but the data after @4420 will be set to “FF” to the end of memory. Would you and suggestion how to not modify other flash??
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Forum Post: RE: CCS/TMS320F28379D: ePWM - Interrupt TMS320F28379D
Yes i checked , Also i checked all the register while in debug mode, all seem fine. The problem is, normally TBCTR start counting but it is not happening. so I checked that , whenever i give software force triggering it goes in ISR and TBCTR have some counting. But its not automatically triggering ISR
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Forum Post: RE: CCS/LAUNCHXL2-TMS57012: After distributing flash for bootloader test I am not able to use Interrupt in Application code
My apologies, the "Application Int" project got code generated via Halcogen and the changes which I made in Linker file & interrupt vector table where replaced by Halcogen generated code. You can observe clearly that Interrupt Vector table for both the projects do not use a same settings. The difference is In Application Project : resetEntry b _c_int00 undefEntry b undefEntry svcEntry b svcEntry prefetchEntry b prefetchEntry b _dabort b phantomInterrupt ldr pc,[pc,#-0x1b0] ldr pc,[pc,#-0x1b0] In Bootloader Project: ;resetEntry b _c_int00 undefEntry b undefEntry svcEntry b svcEntry prefetchEntry b prefetchEntry b _dabort b phantomInterrupt ldr pc,[pc,#-0x1b0] ldr pc,[pc,#-0x1b0] The change is resetEntry is not commented in Application Project.
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Forum Post: CCS/TMS320F28379D: #TMS320F28379D #C2000 WARE #IPC #BOOT
Part Number: TMS320F28379D Tool/software: Code Composer Studio Hi, I am trying to synchronize both my CPU01 and CPU02 using the IPC flags .I am running both the codes on their respective RAMs.The problem is the below line IpcRegs.IPCSET.bit.IPC17 = 1; is not getting set to one , that is IPC17 bit is not getting set to one in CPU02 code . i have attached both codes below . (Please visit the site to view this file) (Please visit the site to view this file) Regards, Ashwin
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Forum Post: RE: CCS/CODECOMPOSER: How to read high memory from CCS plugin
Hi, I am sorry that I can't understand the plugin. But in MSP430, the assembly code to access the 20-bit address is quite different from 16-bit. You can refer to this picture. For more information, you can look into our user guide. Eason
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Forum Post: RE: CCS/LAUNCHXL2-TMS57012: After distributing flash for bootloader test I am not able to use Interrupt in Application code
I have got the interrupt based application code running properly. Also, the program is jumping from Bootloader to Interrupt based Application properly. This was resolved by changing the application linker file as per you recommended. I have attached edited projects please have a look. I also have another query which is as follows, The interrupt vector file which I am using for Bootloader is: ;resetEntry b _c_int00 undefEntry b undefEntry svcEntry b svcEntry prefetchEntry b prefetchEntry b _dabort b phantomInterrupt ldr pc,[pc,#-0x1b0] ldr pc,[pc,#-0x1b0] And Can based bootloader Example is using: [Have also attached the can based example.] b _c_int00 ;0x00 b #0x1FFF8 ;0x04 b #0x1FFF8 ;0x08, Software interrupt b #0x1FFF8 ;0x0C, Abort (prefetch) b #0x1FFF8 ;0x10, Abort (data) reservedEntry b reservedEntry ;0x14 ldr pc,[pc, #-0x1b0] ;0x18 ldr pc,[pc, #-0x1b0] ;0x1C What is the difference? How can I understand what each line is doing? And also you haven't given any reference documentation which will help me edit interrupt vector file (sys_intvecs.asm). Please provide me with the same. (Please visit the site to view this file) (Please visit the site to view this file)
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Forum Post: RM48L952: issue about RXSOFOVERRUNS
Part Number: RM48L952 Hi ALL: How can I clear the register RXSOFOVERRUNS, when overrun has occurred. Thanks and regards
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Forum Post: CCS/TMS320F28069M: Motor makes sounds if stop in movement
Part Number: TMS320F28069M Tool/software: Code Composer Studio Hello We use TMS320F28069M and two BOOSTXL-DRV8305EVM to drive two Low Inductance PMSM motors in lab 6e. The motors are spinning fine and have been identified in lab 2c and 3a. The problem is when the motors reaches the end of the possible movement the motor still contines to run and makes clicking sounds if velocity is set constant. This is a error case but can still happen and a recalibration is to be performed but whanted is not the motors to click but instead have a smoth slow down when a load is detected. We have HALL sensors that detect the stop in movement and stops velocity. But the clicking sound is still heard before motor stops. Have tried to change the bandwith, MaxAccel and MaxJrk without success. Have not a available current probe to show but took Iq_A of the two motors whick goes into current limit of 5A: I also attach one of the user.h files (which are the same except the Rr, Rs, Ls_d and LS_q which differs: (Please visit the site to view this file) Any help appreciated. Thanks
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Forum Post: TMS320F280049: Ask for FFT example
Part Number: TMS320F280049 Hi I see C2000 can do FFT algorithm on 1. VCU 2. TMS320F387X FFT example：C:\ti\ C2000Ware _1_00_06_00_Software\libraries\dsp\FPU\c28\examples\fft， What's the difference? Do FFT by hardware or look-up table. Based on TMS320F280049 , which project example is the best to start? The purpose is sampling ADC data, then do digital filtering and FFT calculation.
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Forum Post: MSP430F2012: User Guide for MSP430F2012
Part Number: MSP430F2012 Hello ...., I would like to develop an I2C slave program suitable for a MSP430F2012 . I have a User Guide SLAU144i Revised January 2012. There is a newer User Guide Revised July 2013. This document is different in relation to I2C-Mode (Chapter 14 January 2012 compared with Chapter 17 July 2013). The Software-Examples also are not suitable for chapter "User Guide Revison July 2013, I2C-Mode". Is there a newer Release " MSP430F2012 " with a newer I2C-Modul? Regards Jurgen
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Forum Post: CCS/MSP432P401R: CCS v8.3.0 Problems with Serial Terminal and CR
Part Number: MSP432P401R Tool/software: Code Composer Studio Hello, I just updated CCS from v7.4.0 to v8.3.0 in a 64 bit Linux VM for my microcontroller classes next summer semester. I am using the MSP432 Launchpads. When connecting a serial Terminal (View->Terminal) to /dev/ttyACM0, I noticed that no carriage returns (CR) are processed by the Terminal. Using a external serial monitor program (gtkterm) the output is shown correctly. So the boards DO send the CR via the serial interface, but the Terminal view does not process them correctly. Without CR, the output is quite garbled and not readable. Could this be verified and fixed? My students are using the Terminal quite a lot for outputting text/debug messages during their practial exercises. Best regards, Andreas
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Forum Post: MSP430G2553: Problem with non-volatile flash memory and mspflash.h library
Part Number: MSP430G2553 Hello. I know, that this should better be posted on 43oh.com forum, but I got no answer from there. I have wrote a simple Energia program for digital potentiometer control with incremental rotary encoder. They are connected to MSP430G2553 launchpad. I want to save variable "counter" (it is an integer number from 0-255) in non-volatile memory using mspflash.h library in case of reset or power interrupt. But it doesn't saves it. I am allmost sure there is something wrong with initialization of variables or pointers inside my code. Can anyone help? Any improvements in code? My code: #include #include "MspFlash.h" #define outputA P2_1 #define outputB P2_2 #define flash SEGMENT_D int aState; int aLastState; const int slaveSelectPin = SS; const int shutDownPin = P1_4; int pos=0; int counter=0; int p=0; void setup() { pinMode (outputA,INPUT_PULLUP); pinMode (outputB,INPUT_PULLUP); aLastState = digitalRead(outputA); pinMode (slaveSelectPin, OUTPUT); pinMode (shutDownPin, OUTPUT); SPI.begin(); digitalWrite(shutDownPin, HIGH); digitalPotWrite(1, 0); } void loop() { Flash.read(flash+(pos * sizeof(int)), (unsigned char*)&p, sizeof(int)); aState = digitalRead(outputA); if (aState != aLastState){ if (digitalRead(outputB) != aState) { counter=++counter; } else { counter=--counter; } } if (counter 255) { digitalPotWrite(1, 255); counter = 255; Flash.erase(flash); Flash.write(flash+(pos * sizeof(int)), (unsigned char*)&counter, sizeof(int)); } aLastState = aState; } int digitalPotWrite(int address, int value) { digitalWrite(slaveSelectPin,LOW); SPI.transfer(address); SPI.transfer(value); digitalWrite(slaveSelectPin,HIGH); } Thank you in advance, Superpanky
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Forum Post: TMS320F28069M: Not able to generate PIL model from subsystem
Part Number: TMS320F28069M Hello, I am working on simulink, want to generate PIL block from the subsystem. whenever I tried to generate PIL block I am getting this on the diagnostics window:- Generating code into build folder: D:\ASH_pc2\MATLAB_workspace\PANVA\mil_new\Subsystem1_ert_rtw #4169 has an unconditional transition '{PM_State=1}' that shadows the following transitions: '[PM_Status== 5]' You can also configure the diagnostic by clicking here. [6 similar] Component:Stateflow | Category:Coder warning Junction #4178 does not have an unconditional path to a state or a terminal junction AND it has multiple paths leading to it. This might lead to confusing run-time behavior because of the backtracking semantics of Stateflow. In particular: 1. The transitions downstream of this junction might get executed multiple times (depending on the number of incident paths to this junction). 2. Execution might backtrack all the way to another transition upstream of this junction leading to execution of undesired transitions. To avoid this potentially confusing behavior, consider adding an unconditional transition to a terminal junction from this junction #4178 . This will ensure that execution never backtracks from this junction. Type "sfhelp('backup_warning_error')" for more examples of undesirable backtracking semantics. You can also configure the diagnostic by clicking here. [9 similar] Component:Stateflow | Category:Coder warning The data 'Mode' has an 8 bit data type. However the 'Hardware Implementation' section of Configuration Parameters has no 8 bit data type. This may cause simulation results to not match code generation results in case the 8-bit computation overflows. [14 similar] Component:Stateflow | Category:Coder warning Model sample time is set to 1e-05 sec, which is longer than this threshold. Transition 'after(2,usec)' in Chart 'Subsystem1/Subsystem1/Chart' : after(2,usec) [4 similar] Component:Stateflow | Category:Coder warning ### Invoking Target Language Compiler on Subsystem1.rtw ### Using System Target File: C:\Program Files\MATLAB\R2018b\rtw\c\ert\ert.tlc ### Loading TLC function libraries ...... ### Generating TLC interface API for custom data .. ### Initial pass through model to cache user defined code ....... ### Caching model source code ............................................................................... ............................................................................... ........ ### Writing header file Subsystem1_types.h ### Writing source file Subsystem1.c ### Writing header file Subsystem1_private.h ### Writing header file Subsystem1.h . ### Writing header file rtwtypes.h ### Writing header file rtmodel.h ### TLC code generation complete. ### Evaluating PostCodeGenCommand specified in the model ### Using toolchain: Texas Instruments C2000 Code Generation Tools v16.9.2 | gmake (64-bit Windows) ### Creating 'D:\ASH_pc2\MATLAB_workspace\PANVA\mil_new\Subsystem1_ert_rtw\Subsystem1.mk' ... ### Successful completion of code generation for model: Subsystem1 ### Creating HTML report file Subsystem1_codegen_rpt.html Build process completed successfully But it not generating PIL model for the same. Please help me, I have tried many solutions but stuck Thanks
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Forum Post: CCS/SM320F28335-EP: Troubles with watchdog
Part Number: SM320F28335-EP Tool/software: Code Composer Studio Hi all, I have problems configuring the watchdog module in this specific device: here are my definitions: /* PLL Status Register */ struct PLLSTS_BITS { /* bits description */ uint16_t PLLLOCKS:1; /* 0 PLL lock status */ uint16_t rsvd1:1; /* 1 reserved */ uint16_t PLLOFF:1; /* 2 PLL off bit */ uint16_t MCLKSTS:1; /* 3 Missing clock status bit */ uint16_t MCLKCLR:1; /* 4 Missing clock clear bit */ uint16_t OSCOFF:1; /* 5 Oscillator clock off */ uint16_t MCLKOFF:1; /* 6 Missing clock detect */ uint16_t DIVSEL:2; /* 7 Divide Select */ uint16_t rsvd2:7; /* 15:7 reserved */ }; union PLLSTS_REG { uint16_t all; struct PLLSTS_BITS bit; }; /* High speed peripheral clock register bit definitions: */ struct HISPCP_BITS { /* bits description */ uint16_t HSPCLK:3; /* 2:0 Rate relative to SYSCLKOUT */ uint16_t rsvd1:13; /* 15:3 reserved */ }; union HISPCP_REG { uint16_t all; struct HISPCP_BITS bit; }; /* Low speed peripheral clock register bit definitions: */ struct LOSPCP_BITS { /* bits description */ uint16_t LSPCLK:3; /* 2:0 Rate relative to SYSCLKOUT */ uint16_t rsvd1:13; /* 15:3 reserved */ }; union LOSPCP_REG { uint16_t all; struct LOSPCP_BITS bit; }; /* Peripheral clock control register 0 bit definitions: */ struct PCLKCR0_BITS { /* bits description */ uint16_t rsvd1:2; /* 1:0 reserved */ uint16_t TBCLKSYNC:1; /* 2 EWPM Module TBCLK enable/sync */ uint16_t ADCENCLK:1; /* 3 Enable high speed clk to ADC */ uint16_t I2CAENCLK:1; /* 4 Enable SYSCLKOUT to I2C-A */ uint16_t SCICENCLK:1; /* 5 Enalbe low speed clk to SCI-C */ uint16_t rsvd2:2; /* 7:6 reserved */ uint16_t SPIAENCLK:1; /* 8 Enable low speed clk to SPI-A */ uint16_t rsvd3:1; /* 9 reserved */ uint16_t SCIAENCLK:1; /* 10 Enable low speed clk to SCI-A */ uint16_t SCIBENCLK:1; /* 11 Enable low speed clk to SCI-B */ uint16_t MCBSPAENCLK:1; /* 12 Enable low speed clk to McBSP-A */ uint16_t MCBSPBENCLK:1; /* 13 Enable low speed clk to McBSP-B */ uint16_t ECANAENCLK:1; /* 14 Enable system clk to eCAN-A */ uint16_t ECANBENCLK:1; /* 15 Enable system clk to eCAN-B */ }; union PCLKCR0_REG { uint16_t all; struct PCLKCR0_BITS bit; }; /* Peripheral clock control register 1 bit definitions: */ struct PCLKCR1_BITS { /* bits description */ uint16_t EPWM1ENCLK:1; /* 0 Enable SYSCLKOUT to EPWM1 */ uint16_t EPWM2ENCLK:1; /* 1 Enable SYSCLKOUT to EPWM2 */ uint16_t EPWM3ENCLK:1; /* 2 Enable SYSCLKOUT to EPWM3 */ uint16_t EPWM4ENCLK:1; /* 3 Enable SYSCLKOUT to EPWM4 */ uint16_t EPWM5ENCLK:1; /* 4 Enable SYSCLKOUT to EPWM5 */ uint16_t EPWM6ENCLK:1; /* 5 Enable SYSCLKOUT to EPWM6 */ uint16_t rsvd1:2; /* 7:6 reserved */ uint16_t ECAP1ENCLK:1; /* 8 Enable SYSCLKOUT to ECAP1 */ uint16_t ECAP2ENCLK:1; /* 9 Enable SYSCLKOUT to ECAP2 */ uint16_t ECAP3ENCLK:1; /* 10 Enable SYSCLKOUT to ECAP3 */ uint16_t ECAP4ENCLK:1; /* 11 Enable SYSCLKOUT to ECAP4 */ uint16_t ECAP5ENCLK:1; /* 12 Enable SYSCLKOUT to ECAP5 */ uint16_t ECAP6ENCLK:1; /* 13 Enable SYSCLKOUT to ECAP6 */ uint16_t EQEP1ENCLK:1; /* 14 Enable SYSCLKOUT to EQEP1 */ uint16_t EQEP2ENCLK:1; /* 15 Enable SYSCLKOUT to EQEP2 */ }; union PCLKCR1_REG { uint16_t all; struct PCLKCR1_BITS bit; }; /* Peripheral clock control register 2 bit definitions: */ struct PCLKCR3_BITS { /* bits description */ uint16_t rsvd1:8; /* 7:0 reserved */ uint16_t CPUTIMER0ENCLK:1; /* 8 Enable SYSCLKOUT to CPU-Timer 0 */ uint16_t CPUTIMER1ENCLK:1; /* 9 Enable SYSCLKOUT to CPU-Timer 1 */ uint16_t CPUTIMER2ENCLK:1; /* 10 Enable SYSCLKOUT to CPU-Timer 2 */ uint16_t DMAENCLK:1; /* 11 Enable the DMA clock */ uint16_t XINTFENCLK:1; /* 12 Enable SYSCLKOUT to XINTF */ uint16_t GPIOINENCLK:1; /* Enable GPIO input clock */ uint16_t rsvd2:2; /* 15:14 reserved */ }; union PCLKCR3_REG { uint16_t all; struct PCLKCR3_BITS bit; }; /* PLL control register bit definitions: */ struct PLLCR_BITS { /* bits description */ uint16_t DIV:4; /* 3:0 Set clock ratio for the PLL */ uint16_t rsvd1:12; /* 15:4 reserved */ }; union PLLCR_REG { uint16_t all; struct PLLCR_BITS bit; }; /* Low Power Mode 0 control register bit definitions: */ struct LPMCR0_BITS { /* bits description */ uint16_t LPM:2; /* 1:0 Set the low power mode */ uint16_t QUALSTDBY:6; /* 7:2 Qualification */ uint16_t rsvd1:7; /* 14:8 reserved */ uint16_t WDINTE:1; /* 15 Enables WD to wake the device from STANDBY */ }; union LPMCR0_REG { uint16_t all; struct LPMCR0_BITS bit; }; /* Dual-mapping configuration register bit definitions: */ struct MAPCNF_BITS { /* bits description */ uint16_t MAPEPWM:1; /* 0 EPWM dual-map enable */ uint16_t rsvd1:15; /* 15:1 reserved */ }; union MAPCNF_REG { uint16_t all; struct MAPCNF_BITS bit; }; /* SYS_CTRL_REGS */ #ifdef __cplusplus #pragma DATA_SECTION("SysCtrlRegsFile") #else #pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); #endif struct SYS_CTRL_REGS SysCtrlRegs; /* END SYS_CTRL_REGS */ /* System Control Register File: */ struct SYS_CTRL_REGS { uint16_t rsvd1; /* 0 */ union PLLSTS_REG PLLSTS; /* 1 */ uint16_t rsvd2[8]; /* 2-9 */ union HISPCP_REG HISPCP; /* 10: High-speed peripheral clock pre-scaler */ union LOSPCP_REG LOSPCP; /* 11: Low-speed peripheral clock pre-scaler */ union PCLKCR0_REG PCLKCR0; /* 12: Peripheral clock control register */ union PCLKCR1_REG PCLKCR1; /* 13: Peripheral clock control register */ union LPMCR0_REG LPMCR0; /* 14: Low-power mode control register 0 */ uint16_t rsvd3; /* 15: reserved */ union PCLKCR3_REG PCLKCR3; /* 16: Peripheral clock control register */ union PLLCR_REG PLLCR; /* 17: PLL control register */ /* No bit definitions are defined for SCSR because */ /* a read-modify-write instruction can clear the WDOVERRIDE bit */ uint16_t SCSR; /* 18: System control and status register */ uint16_t WDCNTR; /* 19: WD counter register */ uint16_t rsvd4; /* 20 */ uint16_t WDKEY; /* 21: WD reset key register */ uint16_t rsvd5[3]; /* 22-24 */ /* No bit definitions are defined for WDCR because */ /* the proper value must be written to the WDCHK field */ /* whenever writing to this register. */ uint16_t WDCR; /* 25: WD timer control register */ uint16_t rsvd6[4]; /* 26-29 */ union MAPCNF_REG MAPCNF; /* 30: Dual-mapping configuration register */ uint16_t rsvd7[1]; /* 31 */ }; extern struct SYS_CTRL_REGS SysCtrlRegs; and in my DSP2833x_Headers_nonBIOS.cmd I defined as follow: MEMORY { PAGE 1 ... SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ ... } SECTIONS { ... /*** Peripheral Frame 2 Register Structures ***/ SysCtrlRegsFile : > SYSTEM, PAGE = 1 ... } /* End of file*/ I'm sure that the ranges entered above are correct because in debug mode I can visualize every field pointing to the correct address. However my problem is when I try to change for instance the SysCtrlRegs.WDCR. This register does never change !! Here is the procedure that I follow: __asm(" EALLOW"); ... ... SysCtrlRegs.WDCR = 0x0068; ... ... ... __asm(" EALLOW"); I also tried to modify the register's value in debug mode (Code Composer Studio v 8.3.0) but the behaviour is the same. An other thing that I'm not understanding is that other fields in the structure SysCtrlRegs can be modified without any kind of problem.. Any help would be appreciated. Sorry for the length of my post and my bad english, but I'm not a native speaker :) Hoping in any advice, best regards, Marco.
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