Hi Wang, Question: In the PASS Scenario, what is the value in the ESM status registers before jumping to the 1st image? Answer: PASS Scenario is after loading new image each time we have to power cycle to execute successfully. Thanks, Kalyan
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Forum Post: RE: TMS570LS3137: TMS570LS3137 code loaded using Flash F021 API stuck at CheckFlashECC()
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Forum Post: TMS320F28035: The 15 channel ADC result jumps sometimes
Part Number: TMS320F28035 Hi, Use ADC 15 channel to measure external temp, and output the ADC result by CAN. As on below CAN output result. The good result is around 2601, but it sometimes jumps to 2871. 1. We have checked other ADC channels result but no this similar problem. 2. So, we make hardware ABA test. Connect channel 10 external circuit voltage as input to channel 15. The issue follow with channel number rather than external circuit. On channel 15, the normal ADC result is 115, it jumps to 2871 sometimes. But no this problem on channel 10. 3. Here is the ADC initialization code. (Please visit the site to view this file)
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Forum Post: CCS/TMS320F280049: Breakdown to execute Flash_Init() after select optimization level to "0-Register Optimizations"
Part Number: TMS320F280049 Tool/software: Code Composer Studio Hi CCS 7.2.0.00013 Select optimization level to "0-Register Optimizations" It breakdown to execute Flash_Init() that will jump to an illegal interrupt or prompt an program execution error. After do breakpoint test step by step, we find it breakdown at Fapi_setActiveFlashBank(Fapi_FlashBank1); Also, we open "0-Register Optimizations" on another project, no this issue when execute Flash_Init() and Fapi_setActiveFlashBank(Fapi_FlashBank1) function. What's the reason? Thanks a lot.
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Forum Post: RE: TMS570LC4357: Interfacing on EMIF with asynchronous 2x8bit MRAM (MR4A08BUYS45)
Thank you QJ. Indeed, using external OR gates is not an option in this design, but I am wondering if it could be simply done by defining that all the data READ (this is actually the case since the EMIF_nDQM are always active during READ commands) and WRITE commands must be performed on 16bit strictly. This could be defined as rule in all READ and WRITE accesses to the MRAM. In this configuration, we would exactly use the connection you proposed. Could you confirm that it can be defined in this way, that all the WRITE accesses are always on 16bit and no masking through nDQM signals is used (EMIF_nDQM[1:0] would not be connected and used in the MRAM memories)? Best regards Vincent
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Forum Post: RE: TM4C123GH6PM: Required more no. of QEI for my project
[quote user="Yashwanth Gandeti"] Hi Twelve12pm, Thanks a lot for sharing Chip No. So, according to my requirement I should use 6 chips of this model is it? Regards, Yashwanth Kumar Gandeti [/quote] Each LS7366R provides one QEI, so yes, if you use that and you need 6 QEIs, you would need 6 ICs. It would probably be better for board space, BOM count, etc., if you could find a chip with more QEIs in one IC. If you do find one, please let us know!
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Forum Post: RE: TM4C1294NCPDT: DMA transfer form UART to memory
I think you are already using the best approach. Use interrupts to receive enough bytes to determine the length of the packet and then use uDMA to receive the rest.
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Forum Post: RE: TMS570LC4357: nERROR and nERROR1 and nERROR2 pins
Hi Vincent, Your understanding is correct. ESM1 has an option to show the current status of either nERROR1 or nERROR. By default, PINMMR174[16] is set to 1. This makes ESM1 show the status of nERROR. The output signal could be shown on both nERROR and nERROR1 balls. Note that nERROR1 is not the default output on the assigned ball J2. The default signal output on this ball is GIOB[6]. So, the application should assume that there is no nERROR1 or nERROR2, only nERROR. Also, leave the PINMMR registers dealing with the nERRORx multiplexing in their default states. Regards, Sunil
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Forum Post: RE: TM4C1230E6PM: JTAG Daisy chain configuration
The JTAG TAP is reset at power on, and then can be put into the test reset state by holding TMS high for 5 TCK cycles. The JTAG controller takes care of this without the need for a separate reset signal controlled by the JTAG scan controller.
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Forum Post: RE: TM4C1230E6PM: JTAG Daisy chain configuration
Termination on TCK is most important as reflections will be seen as an extra clock pulse and will cause the JTAG controller to be out of sync with the device. Proper termination on TMS, and TDI can help achieve higher speeds, but is not critical at lower scan speeds. It is important that you avoid cross talk on all JTAG signals. This is usually an issue in the cabling, not so much in board layout.
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Forum Post: RE: CCS/LAUNCHXL2-RM57L: Debug Problem
Amar, Is this the entire program being loaded into the flash? Do you have any initialization code before the execution jumps to the main() function? CCS looks for a label called "main" by default as a breakpoint upon loading and executing any program. Do you have this feature disabled? I would recommend creating a CCS project starting from HALCoGen , as described in this application note: www.ti.com/.../spna121b.pdf You can also refer to a video and step-by-step instructions on this page for more information: processors.wiki.ti.com/.../Creating_new_CCS_v5_Project_with_HALCoGen
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Forum Post: TMS320F28377D: Triggering scheme SPI/DMA for external ADC
Part Number: TMS320F28377D Hi all, I'm trying to interface a F28377D to an external 16b ADC (LTC2378-16), goal is to have the result available in RAM within 1us of triggering a conversion. Overall I'm looking at a scheme very similar to that described in this post , though I intend to use the normal SPI instead of McBSP (since SPI can operate up to 50MHz in high speed mode). I intend to generate the CNV pulses using ePWM. In the linked example, the author uses two DMA channels, first to start the SPI transaction (triggered via XINT by the ADC's busy signal) and another to move the received data to RAM. My question is if there is an alternative that doesn't require using a valuable DMA channel to trigger a dummy transition. Is it perhaps possible to trigger the SPI via XINT, or by a PWM event? Software triggering using an interrupt is not an option here.
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Forum Post: RM46L852: EQEP - setting up
Part Number: RM46L852 Hello, me again. Once more, I have a question, but this time about eQEP periphery and I hope you can help me out with this one. I got an encoder and wired it up to TI Hercules controller. Specifically, I took 5V, GND EQEP1A and EQEP1B and wired them up. I completely ignored the INDEX channel of the encoder. I have problem with eQEP and I do not understand how to use it, so I hope you can help me. I've enabled EQEP DRIVER. In PINMUX I've enabled EQEP1A and EQEP1B. In EQEP1 I've set all according to the provided example: QUADRATURE COUNT, RESOLUTION 2X, ENABLED SW INITIALISATION (what is this?), SET INIT TO 0 AND MAX TO 0xFFFF_FFFF. CAPTURE TIME POS MOD - ON UNIT TIMEOUT EVENT (enabled Unit Timeout Interrupt as well). This is the Code Composer Studio code I have: int main(void) { /* USER CODE BEGIN (3) */ uint16 deltaT = 0U; float velocity = 0U; /* EQEP initialization based on GUI Configuration. */ QEPInit(); /* Enable Position Counter */ eqepEnableCounter(eqepREG1); /* Enable Unit Timer. */ eqepEnableUnitTimer(eqepREG1); /* Enable capture timer and capture period latch. */ eqepEnableCapture(eqepREG1); while(1) { /* Status flag is set to indicate that a new value is latched in the QCPRD register. */ if((eqepREG1->QEPSTS & 0x80U) !=0U) { /* Elapsed time between unit position events */ deltaT = eqepREG1->QCPRD; /* Calculate Velocity from deltaT and the value of the unit position. */ /* The value of Unit Position is a sample value and should be changed by the * User as per the actual value in the UNIT_POSITION_X macro above. */ velocity = (float)(UNIT_POSITION_X/deltaT); /* Clear the Status flag. */ eqepREG1->QEPSTS |= 0x80U; printf ("VELOCITY >> %f \n", velocity); printf ("COUNTER >> %u \n", eqepREG1->QPOSLAT); } } I've added to print velocity and position counter. When I try to move encoder these are the results I get: Move 1: VELOCITY >> 0.000000 COUNTER >> 1 VELOCITY >> 0.000000 COUNTER >> 1 Move 2: VELOCITY >> 0.000000 COUNTER >> 0 VELOCITY >> 0.000000 COUNTER >> 0 Move 3: VELOCITY >> 0.000000 COUNTER >> 0 VELOCITY >> 0.000000 COUNTER >> 0 Move 4: VELOCITY >> 0.000000 COUNTER >> 1 VELOCITY >> 0.000000 COUNTER >> 2 Move 5: VELOCITY >> 0.000000 COUNTER >> 2 VELOCITY >> 0.000000 COUNTER >> 2 VELOCITY >> 0.000000 COUNTER >> 3 If I move encoder once, it will get into if not once, but usually two times (last case, it entered into IF three times). If I turn it for 5deg it is the same as if I turned it for 100deg. Value in QPOSLAT register barely changes. It changes for one or non increment. I cannot understand why... Also, velocity is always 0.000000. This never changes. Why? I've tried incrementing Unit Init Period from 0x0000_0001 up to 0xFFFF_FFFF but haven't had any success. I would like to use encoders with 300 rpms. So, from them I need two sets of information: (1) Time between previous and current position change -> to determine velocity (2) Incremented values so I have knowledge about position. Can you help me out? Thanks, Marc :)
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Forum Post: RE: RM46L852: N2HET as GIO interrupts
QJ Wang, Thank you for your reply! :) I completely understood what I've been missing. :) Just one quick additional question. Am I blind or are there no interrupts: HET1 Level 0 and Level1?
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Forum Post: RE: TMS570LC4357: CRC Algorithm
Hi Jens, The TI CodeGen tools include an ability to generate CRC tables for initialized sections. Please refer to the ARM assembly tools user guide here for more details: downloads.ti.com/.../ Section 8.9 specifically explains the usage of this feature. Also refer to this blog explaining how to use this capability to perform cyclic redundancy checking using linker-generated CRC tables: e2e.ti.com/.../from-the-experts-perform-cyclic-redundancy-checking-using-linker-generated-crc-tables This includes a video demonstrating the operation. It is specific to a C2000 MCU, but can be easily adapted for the TMS570 MCUs. I will also look to create an example specific for TMS570 MCUs. Hope this helps in the mean time. Regards, Sunil
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Forum Post: CCS/LAUNCHXL-F28379D: Programming the 2 CPU of LAUNCHXL-F28379D
Part Number: LAUNCHXL-F28379D Tool/software: Code Composer Studio Hello Everybody, I am trying to use 3 SPIs of Delfino both processors but i don't know the right steps. For example, should i write one program and burn this program to both CPUs ? if yes, is there a directive for programming one CPU (eg: #define CPU1) at a time? or master CPU has different configuration than the other one? if yes, is there any tutorial i can relay on? regards
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Forum Post: TMS570LC0714 with flash F021 API
Hi, I am working with the TMS570LC0714 Controller. I want to program a boot loader software which can erase and program the flash bank 0. But I have problems to erase the flash area. So what I know is that the fapi functions must run in RAM area if I want to erase flash section of bank 0. The following points are showing what I have done: 1.) I use the controller without floating point unit, so I used the Lib "F021_API_CortexR4_BE.lib". Hope it is the right one. 2.) I adapted the Linker command file as followed: VECTORS (X) : origin=0x00000000 length=0x00000020 FLASH_API (RX) : origin=0x00000020 length=0x000014E0 FLASH0 (RX) : origin=0x00001500 length=0x0001EB00 STACKS (RW) : origin=0x08000000 length=0x00001500 RAM_API (RWX): origin=0x08001500 length=0x0000EB00 RAM (RW) : origin=0x08010000 length=0x00010000 AJSM (RX) : origin=0xF0000000 length=0x00000010 flashapi : { --library= F021_API_CortexR4_BE.lib (.text) } LOAD = FLASH_API, RUN = RAM_API, LOAD_START(FlashApi_LoadStart), RUN_START(FlashApi_RunStart), SIZE(FlashApi_LoadSize) 3.) I copied all Flash data into RAM before I want to erase the flash as followed: void CopyApiFromFlashToRam(void) { uint32 size; uint32 i; size = (uint32)&FlashApi_LoadSize; for(i=0;i<size;i++) { ((char *)&FlashApi_RunStart)[i] =((char *)&FlashApi_LoadStart)[i]; } } 4.) My function to erase the flash is called Fapi_BlockErase (Flash area). The following map file listing shows the Fapi functions with the corresponding Flash / RAM address. 000086d0 Fapi_BlockErase All fapi functions are in RAM area, also the Fapi_serviceWatchdogTimer function. 08001c49 Fapi_calculateEcc 08001bc5 Fapi_calculateFletcherChecksum 08001a55 Fapi_enableEepromBankSectors 08001ad5 Fapi_enableMainBankSectors 08001c5d Fapi_getNumberOfBankSectors 08001501 Fapi_initializeFlashBanks 08001bfd Fapi_issueAsyncCommandWithAddress 080018dd Fapi_issueProgrammingCommand 08001c8c Fapi_serviceWatchdogTimer 08001761 Fapi_setActiveFlashBank 00000794 FlashApi_LoadSize 00000020 FlashApi_LoadStart 08001500 FlashApi_RunStart But it is still not erasing the flash. Any ideas ? Best regards bruno
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Forum Post: RE: MSP430FR2311: FRAM variable writes
Eddie, There is no MPU tab, that is why I am confused. I'm running CCS8.3 and the out of box demo from the resource explorer.
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Forum Post: RE: TMS570LS3137-EP: TMS570LS3137 FLASH
Hi Rajeeva, the application engineer supporting this device is out of office due to the holidays. He will reply to your e-mail after he returns on the 2nd. Thanks, JV
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Forum Post: RE: CCS/MSP432P401R: -
Resetting with S3 on MSP-EXP432P401R and continued without verified connection. A question of firmware update was asked. After this it worked. Thank You
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Forum Post: RE: MSP430FR2311: FRAM variable writes
[quote user="Andrew5821"]There is no MPU tab, that is why I am confused.[/quote]The MPU tab is only present for FRAM device families which have the MPU, such as the FR59xx series. Where the MPU allows main memory partitioning which is programmable with up to three segments in steps of 1KB. The MSP430FR2311 doesn't have a MPU, and the SYSCFG0 register only allows FRAM write protection to apply to the whole of the program memory (i.e. no memory partitioning as with a MPU).
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