Part Number: TMS320F28379D Hi, I am trying to perform SPI communication between F28379D launchpad (Master) and F28379D ControlCard (Slave). I have written the code following the SPI loopback example shipped in ControlSuite . I configure the master to send a counter data continuously over SPI and slave is configured to read the received data continuously. During transmit I ensure TXFFST is empty before placing the new data on SPITXBUF and while receiving I will check RXFFST if new data is available before reading the data from SPIRXBUF. When I configure both master and slave either as rising edge-no delay or as falling edge-delay half cycle clock modes, I can see the data is received properly in slave. But if I configure both master and slave either as rising edge-half cycle delay or as falling edge-no delay, I am not able to read properly from SPIRXBUF. In these cases, SPIDAT is updated by the received data regularly but the data from SPIDAT is not loaded properly into SPIRXBUF and RXFFST is zero (attached snapshot). Also the SIMO data along with clock and CS is present and can be confirmed using CRO (attached screenshot) and the SIMO data observed in CRO matches with the data observed in SPIDAT. If I replace the slave with other board like F28075 i can see the data being received properly in SPIRXBUF. Can you check once and let me know the reason for this issue? I have attached the code used for both master and slave for the reference. Thanks, Aditya SPI Master (Please visit the site to view this file) SPI Slave (Please visit the site to view this file)

Part Number: MSP430FR6989 Hello, I noticed that i am capable of configuring SPI module with only two options: 3 pin mode (MISO,MOSI,CLK) 4 pin mode (MISO,MOSI,CLK,SS) what if need more than only one "SS" ? Is it OK to simply use GPIO as SS ?

could you please try the sample code adc_temp.c to check if the temp sensor is working properly? best regards Lukas

Any updates Wang?

1) Ok 2) It's not hardware cos i'm tried to flash correctly working device (serially manufactured and tested with old .hex) Thank you

I've run some more tests, with my clock_init() function resembling the example; and it worked - for a while. I then changed some settings in a spi_init() function elsewhere and the clocks went weird again. Notably, MCLK changed to 1MHz and SMCLK went to ~72kHz.

Hi Archie, in the MSPDS package following the path: MSPDS >DLL430_v3>include you can find the "MSP430_ EnergyTrace .h" file. This is showing you starting at line 56 the definitions for the Bit fields and data in the debug communication, please see here below. *********************************************************************************************************************************** /* Record format ------------- The default record format for operation mode 1 for the MSP430FR5859 is 22bytes for each record consisting of: [8byte header][8byte device State][4byte current I in nA][2byte voltage V in mV][4byte energy E in uWsec= 100 nJ] Where the header consists of: [1byte eventID][7byte timestamp in usec] The eventID defines the number of arguments following the header. eventID = 1 : I value, 32 bits current eventID = 2 : V value, 16 bits voltage eventID = 3 : I & V values, 32 bits current, 16 bits voltage eventID = 4 : S value, 64 bits state (default type for ET_PROFILING_DSTATE) eventID = 5 : S & I values, 64 bits state, 32 bits current eventID = 6 : S & V values, 64 bits state, 16 bits voltage eventID = 7 : S & I & V & E values, 64 bits state, 32 bits current, 16 bits voltage, 32 bits energy (default type for ET_PROFILING_ANALOG_DSTATE) eventID = 8 : I & V & E values, 32 bits current, 16 bits voltage, 32 bits energy (default type for ET_PROFILING_ANALOG) eventID = 9 : S & I & V values, 64 bits state, 32 bits current, 16 bits voltage ********************************************************************************************************************************************************************** You can find more details on the bits related to Energy Trace and the other data in the MSPDebugStack Developer's Guide SLAU656B. Best regards Peter

Hello QJ Wang, Thanks for your reply. I have tried everything as per your instruction. But the problem is not resolved. I have purchased a new board to continue my work. One last thing I want to ask is what may be the reason for this error (The first screenshot). So far I have read many TI forums and I have come to conclusion that the bootloader may get corrupted. Am I right? Or is there any other reason? Thanks and Regards, Saurabh Shah, CoEP

Santosh, I checked HW configuration for EMIF in HAL SW and it looks good. Below screens from my CCS and schematics: LaunchPad J9 HighDensity connector: TIDM-DELPHINO_ETHERCAT J6 HighDensity connector: As you can see on pin 49 it's GPIO107 which is on my configuration below: Santosh, what should I check next? BR, Dawid.

Part Number: TMS320F28379D Tool/software: Code Composer Studio Hello everyone, I am running then EtherCat Stack supplied by ControlSuite and after checking that it works properly I applied both in RAM and FLASH, I applied some snippets in it to initialize and use 2 ePwm signals, 2 eQep singals and 2 adc. However I encounter a certain problem when I try to execute the code from flash (in RAM it works perfectly fine). It jumps into ILLEGAL ISR routine at this specific part of the EtherCat stack that it didn't before enabling the aforementioned peripherals The cmd file is excluded from build in both RAM and FLASH configurations by the default ControlSuite Program and the HW_Init() function which is not causing any problem is the following: //############################################################################# // // FILE: ethercat_slave_c28x_hal.c // // TITLE: C28x HAL level functions for EtherCAT slave controller (ESC) // //! \addtogroup C2k_EtherCAT_adapater_examples_list //! PDI Interface test Example //! //! The functions in this file provide a HAL layer interface for EtherCAT slave //! applications that can be built on C2k EtherCAT adapter board //! //! The HAL could be EMIF or SPI based depending on the PDI interface chosen //! or configured for the C2k ET1100 EtherCAT adapater board //! //!----------------------------------------------------------------------------- //! C28x Addressing vs. TwinCat3 software addresses for EMIF PDI //! The C28x address used below is a WORD (16b) address for the ET1100 PDI //! interface, while Beckhoff EtherCAT documentation and TwinCat3 software use //! BYTE addresses. The USER RAM on the ET1100 starts at 0x1000 offset BYTE //! address. Divide this by 2 to get the correct 16b word offset from EMIF2 //! start address //! //! EMIF PDI reads two bytes at a time from ET1100 address space, that is the //! minimum data size thats readable by C28x CPU //!------------------------------------------------------------------------------ //!------------------------------------------------------------------------------ //! C28x Addressing vs. TwinCat3 software addresses for SPI PDI //! For the SPI PDI the addressing of ET1100 memory space is straight forward //! The SPI PDI uses 8 bit character length for SPI reads/writes but the HAL API //! is adjusted to read 16bits at a time to be consistent with the EMIF PDI. //! Users can modify the SPI PDI to read/write one byte at a time from ET1100 //! address space. But since C28x data bus is 16 bit wide this example shows //! 16bit SPI PDI reads/writes as well. //! //! SPI MISO pin read for error status on the last transaction is not supported //! in this HAL //! SPI MODE 3 is supported by this HAL //! I0 and I1 byte reads on the MISO pin are ignored in this HAL //!------------------------------------------------------------------------------ //! \b External \b Connections \n //! Users can connect a PC running TWINCAT3 to the Ethercat Slave and view the //! memory window of ET1100 for both registers and ET1100 RAM //! //! \b Watch \b Variables \n //! - escRegs data structure is filled in with some ET1100 registers which can be //! viewed in memory window if HAL Test is enabled. //! //! ////########################################################################### // $TI Release: C2000 EtherCAT solutions support v1.00 $ // $Release Date: 07/2017 $ // $Copyright: // Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //############################################################################# // // Included Files // #include "F28x_Project.h" // Device Headerfile and Examples Include File #include "F2837xD_spi.h" #include "DCL.h" #include "AdcSetup.h" #include "Posspeed.h" #include "ethercat_slave_c28x_hal.h" // // Defines // //#define ETHERCAT_STACK 1 //only use if EtherCAT slave stack is used // // Global Variables // int AdcaResult0, AdcbResult0, AdcaResult1, AdcbResult1, dc; float analog1 = 0.0f; DCL_PID pid1 = PID_DEFAULTS; float rk1; float yk1; float lk1; float uk1; float Duty1; DCL_PID pid2 = PID_DEFAULTS; float rk2; float yk2; float lk2; float uk2; float Duty2; //eqep POSSPEED qep_posspeed=POSSPEED_DEFAULTS; Uint16 int1cnt = 0; Uint16 int2cnt = 0; float desired_pos_high = 360.0; float desired_pos_low = 0.0; float desired_pos = 360.0; long int raw_pos1, raw_pos2, raw_pos3; long int angle_count1=0; unsigned long int pos_init = 2147483647; //0x7fffffff float gwnia1, gwnia2, gwnia3; float ngwnia1, ngwnia2, ngwnia3; int dir = 0; //Pointer to the ESC memory, initialized in the ESC_initHW() //used only for the ASYNC16 (EMIF1 or EMIF2) PDI //uint16_t *pEsc; #ifdef PDI_HAL_TEST //Debug array to log esc registers, used only for PDI HAL TEST esc_et1100_regs_t escRegs[ESC_DEBUG_REGS_LENGTH]; #endif #ifdef INTERFACE_SPI // SPI Variables volatile uint16_t SPI_RxData[16]; // Receive data buffer volatile uint16_t SPI_XmitInProgress; #endif // //HAL level functions // #ifndef __cplusplus #ifdef INTERFACE_SPI #pragma CODE_SECTION(ESC_readSPI, ".TI.ramfunc"); #pragma CODE_SECTION(ESC_writeSPI, ".TI.ramfunc"); #endif #pragma CODE_SECTION(ESC_timerIncPerMilliSec, ".TI.ramfunc"); #pragma CODE_SECTION(ESC_getTimer, ".TI.ramfunc"); #endif /***********************************************************************************/ //Set the GPyDAT register bit for the specified pin. uint32_t ESC_getTimer(void) { //C28x timer is decrements from 0xFFFFFFFF while the stack understands it as of //increment type. return ~ ((uint32_t)(CpuTimer0Regs.TIM.all)); } /***********************************************************************************/ void ESC_clearTimer(void) { CpuTimer0Regs.TIM.all = 0; } /***********************************************************************************/ uint32_t ESC_timerIncPerMilliSec(void) { return (uint32_t) 200000UL; //at 200MHz } /***********************************************************************************/ // // SPI HAL functions for EtherCAT slave stack // //SPI peripehral register pointer, will be initialized depending on the SPI chosen as per // build configurations volatile struct SPI_REGS *SpixRegs; /***************************************************************************************** * @fn ESC_readSPI * @brief function reads up to 12 bytes of data * * @param * offset_addr - ESC address from which data has to be read * numbytes - number of bytes to be read, limited to 12 at a time by the caller * buffer - pointer to the buffer where read data has to be copied to * - if a NULL is passed then data is copied to SPI_RxData global array * * @return - None ****************************************************************************************/ void ESC_readSPI(uint16_t offset_addr,uint16_t numbytes, uint16_t* buffer) { uint16_t i,cmd, readval, numwords = 0, j; uint16_t *buf = (uint16_t *)0; uint16_t readphase[16]; if(((void *)buffer) == NULL) { buf = (uint16_t *)&SPI_RxData[0]; } else { buf = buffer; } // Construct Address cmd bytes into 16-bit words for SPI xmission, // SPI xmits MSBit 1st, so must swap bytes in this 16b word for transmission // Byte order of READ cmd sequence: // Byte 0: A[12:5] // Byte 1: A[4:0], 110b (110b is 3-byte cmd extension) // Byte 2: A[15:13], CMD[2:0], 00b (011b is READ w/ WS) // Byte 3: FFh (Wait State) //cmd = offset_addr & 0x1f cmd =(offset_addr & 0x1FE0) SPITXBUF = readphase[i] & (0xFF00); SpixRegs->SPITXBUF = ((readphase[i] & (0xFF)) SPIFFRX.bit.RXFFST SPIFFRX.bit.RXFFST != (numbytes)) { ////ignore first two words (4 bytes) readval = SpixRegs->SPIRXBUF; //ignore } for(i=0;((SpixRegs->SPIFFRX.bit.RXFFST != 0));i++) { readval = (SpixRegs->SPIRXBUF) & 0xFF; buf[i]= (readval & 0xFF); readval = (SpixRegs->SPIRXBUF) & 0xFF; buf[i] |= ((readval & 0xFF) SPIFFTX.bit.TXFIFO=0; // Reset Tx FIFO SpixRegs->SPIFFRX.bit.RXFIFORESET = 0; //reset the FIFO pointer DELAY_US(2); SpixRegs->SPIFFTX.bit.TXFIFO=1; // Reenable Tx FIFO SpixRegs->SPIFFRX.bit.RXFIFORESET = 1; //reenable the FIFO operation SPI_XmitInProgress=0; } #define FIFO_LENGTH 12 /***************************************************************************************** * @fn ESC_writeSPI * @brief function writes up to 12 bytes of data * * @param * offset_addr - ESC address to which data has to written to * numbytes - number of bytes to be written to, limited to 12 at a time by the caller * wrdata - pointer to the buffer from where data has to be written to ESC * * * @return - none ****************************************************************************************/ void ESC_writeSPI(uint16_t offset_addr,uint16_t *wrdata, uint16_t numbytes) { uint16_t i, j,cmd, numwords = 0; uint16_t wptr = 0; uint16_t writephase[2]; // Construct Address cmd bytes into 16-bit words for SPI xmission, // SPI xmits MSBit 1st, so must swap bytes in this 16b word for transmission // Byte order of READ cmd sequence: // Byte 0: A[12:5] // Byte 1: A[4:0], 110b (110b is 3-byte cmd extension) // Byte 2: A[15:13], CMD[2:0], 00b (110b is 3-byte cmd extension) // Byte 3: Afirst byte of data //cmd = offset_addr & 0x1f cmd =(offset_addr & 0x1FE0) SPITXBUF = writephase[i] & (0xFF00); SpixRegs->SPITXBUF = ((writephase[i++] & (0xFF)) SPITXBUF = writephase[i] & (0xFF00); SpixRegs->SPITXBUF = ((writephase[i] & (0xFF)) SPITXBUF = ((wrdata[wptr]) & 0xFF00); SpixRegs->SPITXBUF= (((wrdata[++wptr]) & 0x00FF) SPITXBUF = ((wrdata[wptr]) & 0xFF00); numwords++; } SPI_XmitInProgress=1; while(SpixRegs->SPIFFTX.bit.TXFFST != 0) { DELAY_US(2); }; SpixRegs->SPIFFTX.bit.TXFIFO=0; // Reset Tx FIFO SpixRegs->SPIFFRX.bit.RXFIFORESET = 0; //reset the FIFO pointer DELAY_US(2); SpixRegs->SPIFFTX.bit.TXFIFO=1; // Reset Tx FIFO SpixRegs->SPIFFRX.bit.RXFIFORESET = 1; //reenable the FIFO operation SPI_XmitInProgress=0; } /***********************************************************************************/ uint16_t ESC_readWordNonISR(uint16_t offset_addr) { uint16_t data; DINT; ESC_readSPI(offset_addr, 2, &data); EINT; return data; } /***********************************************************************************/ uint16_t ESC_readWordISR(uint16_t offset_addr) { ESC_readSPI(offset_addr, 2, 0); return (SPI_RxData[0]); } /***********************************************************************************/ uint32_t ESC_readDWordNonISR(uint16_t offset_addr) { uint32_t dword; DINT; ESC_readSPI(offset_addr, 4, (uint16_t *)&dword); EINT; return dword; } /***********************************************************************************/ uint32_t ESC_readDWordISR(uint16_t offset_addr) { uint32_t dword; ESC_readSPI(offset_addr, 4, (uint16_t *)&dword); return dword; } /***********************************************************************************/ void ESC_readBlockISR(uint16_t* pData, uint16_t offset_addr,uint16_t numbytes) { uint16_t i = 0, current_bytes = 0, last_byte = 0; if(numbytes & 0x1) { current_bytes = (numbytes - 0x1); // even align } else { current_bytes = numbytes; } while(current_bytes > 0) // input is actually in bytes { if( current_bytes >= FIFO_LENGTH) { ESC_readSPI(offset_addr, FIFO_LENGTH, (uint16_t *) &pData[i]); current_bytes -= FIFO_LENGTH; i+= FIFO_LENGTH/2; // data is in 16 bits offset_addr += FIFO_LENGTH; } else { ESC_readSPI(offset_addr, current_bytes, (uint16_t *) &pData[i]); offset_addr += current_bytes; i+= current_bytes/2; current_bytes = 0; } } if(numbytes & 0x1) { last_byte = ESC_readWordISR(offset_addr); pData[i] = pData[i] & 0xFF00; pData[i] |= last_byte; } } /***********************************************************************************/ void ESC_readBlockNonISR(uint16_t* pData, uint16_t offset_addr,uint16_t numbytes) { DINT; ESC_readBlockISR(pData, offset_addr,numbytes); EINT; } /***********************************************************************************/ void ESC_writeWordNonISR(uint16_t wrdata, uint16_t offset_addr) { DINT; ESC_writeSPI(offset_addr, &wrdata, 0x02); EINT; } /***********************************************************************************/ void ESC_writeWordISR(uint16_t wrdata, uint16_t offset_addr) { ESC_writeSPI(offset_addr, &wrdata, 0x02); } /***********************************************************************************/ void ESC_writeDWordNonISR(uint32_t wrdata, uint16_t offset_addr) { DINT; ESC_writeSPI(offset_addr, (uint16_t *)&wrdata, 0x04); EINT; } /***********************************************************************************/ void ESC_writeDWordISR(uint32_t wrdata, uint16_t offset_addr) { ESC_writeSPI(offset_addr, (uint16_t *)&wrdata, 0x04); } /***********************************************************************************/ void ESC_writeBlockISR(uint16_t* pData, uint16_t offset_addr,uint16_t numbytes) { uint16_t i = 0, current_bytes = 0; if(numbytes & 0x1) { current_bytes = (numbytes - 0x1); // even align } else { current_bytes = (numbytes); } while(current_bytes > 0) // input is actually in bytes { if( current_bytes >= FIFO_LENGTH) { ESC_writeSPI(offset_addr, (uint16_t *) &pData[i], FIFO_LENGTH); current_bytes -= FIFO_LENGTH; i+= FIFO_LENGTH/2; // data is in 16 bits offset_addr += FIFO_LENGTH; } else { ESC_writeSPI(offset_addr, (uint16_t *) &pData[i], current_bytes); offset_addr += current_bytes; i+= current_bytes/2; current_bytes = 0; } } if(numbytes & 0x1) { //now send the last byte with extra alignment bytes // note that we read the adjacent byte and write it back ESC_readSPI(offset_addr, 2, &i); i &= 0xFF00; i |= (pData[((numbytes-1) >> 1)]) & 0xFF; //pData is 16bit pointer ESC_writeSPI(offset_addr, &i, 2); } } /***********************************************************************************/ void ESC_writeBlockNonISR(uint16_t* pData, uint16_t offset_addr,uint16_t numbytes) { DINT; ESC_writeBlockISR(pData, offset_addr,numbytes); EINT; } //----------------------------------------------------------------------------------- // Function to initialize SPI port //----------------------------------------------------------------------------------- void ESC_initSPIFIFO(void) { uint16_t m; EALLOW; // FIFO configuration SpixRegs->SPIFFCT.all=0x0; // place SPI in reset for(m=0;m SPIFFRX.all=0x2040; // RX FIFO enabled, clear FIFO int SpixRegs->SPIFFRX.bit.RXFFIL = 16; // Set RX FIFO level SpixRegs->SPIFFTX.all=0xE040; // FIFOs enabled, TX FIFO released, // SPI configuration SpixRegs->SPIFFTX.bit.TXFFIL = 16; // Set TX FIFO level SpixRegs->SPICCR.bit.SPICHAR = 0x7;//0xF; // Character Length = 8 SpixRegs->SPICCR.bit.CLKPOLARITY = 1; // Rising edge SpixRegs->SPICCR.bit.HS_MODE = 0; // Not high speed mode SpixRegs->SPICTL.bit.SPIINTENA = 1; // Enabled SpixRegs->SPICTL.bit.TALK = 1; // SpixRegs->SPICTL.bit.MASTER_SLAVE = 1; // Master mode SpixRegs->SPICTL.bit.CLK_PHASE = 0; // Add 1/2-cycle delay of Clk wrt SPISTEA SpixRegs->SPICTL.bit.OVERRUNINTENA = 1; // Overrun Interrupt enabled SpixRegs->SPISTS.all=0x0000; // Clear Status bits (TxBufFull,INT, Overrun) // SpixRegs->SPIBRR.all = 0x63; // LSPCLK/100 ClkCfgRegs.LOSPCP.all = 0x1; // 0 = sysclk/1 = 200M; 1 = sysclk/2 = 100M SpixRegs->SPIBRR.all=0x004; // Baud Rate = LSPCLK / (SPIBRR+1) [LSPCLK=SysClk/4 by default=50M] SpixRegs->SPIFFCT.all=0x00; SpixRegs->SPIPRI.all=0x0020; // Stop after transaction complete on EmuStop SpixRegs->SPIFFTX.bit.TXFFIENA = 0; // Disable TXFF INT SpixRegs->SPIFFRX.bit.RXFFIENA = 0; // disable RXFF INT SpixRegs->SPICCR.bit.SPISWRESET=1; // Enable SPI EDIS; } //----------------------------------------------------------------------------------- // Function to initialize GPIOs for SPIB port // GPIO64, GPIO65, GPIO66, GPIO63 // Not used in TMDSECATCNCD379D kit //----------------------------------------------------------------------------------- void ESC_initSPIBGpio(void) { EALLOW; // Enable pull-ups on SPISIMO/SPISOMI/SPICLK/SPISTE pins GpioCtrlRegs.GPCPUD.all &= 0xFFFFFFF8; GpioCtrlRegs.GPBPUD.all &= 0xFFFFFFFE; // Enable SPISIMO/SPISOMI/SPICLK pins GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 0x3; GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 0x3; GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 0x3; GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 0x3; GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 0x3; GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 0x3; GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 0x3; GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0x3; // Enable SPISIMO/SPISOMI/SPICLK pins as async GpioCtrlRegs.GPCQSEL1.all |= 0xF; GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0x3; EDIS; } //----------------------------------------------------------------------------------- // Function to initialize GPIOs for *** port // GPIO122, GPIO123, GPIO124, GPIO125 // Function used in TMDSECATCNCD379D kit //----------------------------------------------------------------------------------- void ESC_initSPICGpio(void) { EALLOW; // new control card with HD connector // Enable pull-ups on SPISIMO/SPISOMI/SPICLK/SPISTE pins //GPIO122,123,124,125 GpioCtrlRegs.GPDPUD.all &= 0xC3FFFFFF; // Enable SPISIMO/SPISOMI/SPICLK pins GpioCtrlRegs.GPDGMUX2.bit.GPIO122 = 0x1; GpioCtrlRegs.GPDGMUX2.bit.GPIO123 = 0x1; GpioCtrlRegs.GPDGMUX2.bit.GPIO124 = 0x1; GpioCtrlRegs.GPDGMUX2.bit.GPIO125 = 0x1; GpioCtrlRegs.GPDMUX2.bit.GPIO122 = 0x2; GpioCtrlRegs.GPDMUX2.bit.GPIO123 = 0x2; GpioCtrlRegs.GPDMUX2.bit.GPIO124 = 0x2; GpioCtrlRegs.GPDMUX2.bit.GPIO125 = 0x2; // Enable SPISIMO/SPISOMI/SPICLK pins as async GpioCtrlRegs.GPDQSEL2.all |= 0x03F00000; EDIS; } //----------------------------------------------------------------------------------- // Function to initialize GPIOs for SPIÁ port // GPIO58(SIMOA), GPIO59(SOMIA), GPIO60(CLKA), GPIO61(SELA) // GPIO16, GPIO17, GPIO18, GPIO19 (commented out) // Not used in TMDSECATCNCD379D kit //----------------------------------------------------------------------------------- void ESC_initSPIAGpio(void) { EALLOW; /* Enable internal pull-up for the selected pins */ // Pull-ups can be enabled or disabled by the user. // This will enable the pullups for the specified pins. Enable pull-ups on SPISIMO/SPISOMI/SPICLK/SPISTE pins GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (SPISIMO-A) GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (SPISOMI-A) GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (SPICLK-A) GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (SPISTE-A) /* Set qualification for selected pins to asynch only */ // This will select asynch (no qualification) for the selected pins. GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58 (SPISIMO-A) GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (SPISOMI-A) GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (SPICLK-A) GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (SPISTE-A) //Configure SPI-A pins using GPIO regs // This specifies which of the possible GPIO pins will be SPI functional pins. //G-Mux GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Enable (SPISIMO-A) GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // Enable (SPISOMI-A) GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Enable (SPISCLK-A) GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // Enable (SPISTE-A) //Mux GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Enable (SPISIMO-A) GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // Enable (SPISOMI-A) GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Enable (SPISCLK-A) GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // Enable (SPISTE-A) EDIS; } /*EALLOW; (OLDER CONFIGURATION from TI for SPI-A and GPIOs 16,17,18,19) // Enable pull-ups on SPISIMO/SPISOMI/SPICLK/SPISTE pins GpioCtrlRegs.GPAPUD.all &= 0xFFF0FFFF; // Enable SPISIMO/SPISOMI/SPICLK pins GpioCtrlRegs.GPAMUX2.all |= 0x00000055; // Enable SPISIMO/SPISOMI/SPICLK pins as async GpioCtrlRegs.GPAQSEL2.all |= 0x0000003F; EDIS; }*/ /***********************************************************************************/ void ESC_releaseET1100Reset(void) { GPIO_SetupPinMux(ESC_RESET_ET1100_GPIO, GPIO_MUX_CPU1, 0); GPIO_WritePin(ESC_RESET_ET1100_GPIO, 1); //release reset } /***********************************************************************************/ void ESC_holdET1100InReset(void) { GPIO_SetupPinMux(ESC_RESET_ET1100_GPIO, GPIO_MUX_CPU1, 0); GPIO_WritePin(ESC_RESET_ET1100_GPIO, 0); //hold in reset } /***********************************************************************************/ void ESC_configureLatch0GPIO(void) { //This function configures SYNC0 GPIO as LATCH OUTPUT (Input to ESC) GPIO_SetupPinOptions(ESC_SYNC0_GPIO, GPIO_OUTPUT, GPIO_PULLUP); GPIO_SetupPinMux(ESC_SYNC0_GPIO, GPIO_MUX_CPU1, 0); } /***********************************************************************************/ void ESC_configureLatch1GPIO(void) { //This function configures SYNC1 GPIO as LATCH OUTPUT GPIO_SetupPinOptions(ESC_SYNC1_GPIO, GPIO_OUTPUT, GPIO_PULLUP); GPIO_SetupPinMux(ESC_SYNC1_GPIO, GPIO_MUX_CPU1, 0); } //----------------------------------------------------------------------------------- // ISR to handle PDI ISR //----------------------------------------------------------------------------------- interrupt void ESC_applicationLayerISR() { //call the slave stack ISR routine #ifdef ETHERCAT_STACK PDI_Isr(); #endif PieCtrlRegs.PIEACK.all |= 0x01; // Issue PIE ack } //----------------------------------------------------------------------------------- // ISR to handle SYNC0 ISR //----------------------------------------------------------------------------------- interrupt void ESC_applicationSync0ISR() { #ifdef ETHERCAT_STACK Sync0_Isr(); #endif //XINT5, PIE 12.INT3 PieCtrlRegs.PIEACK.bit.ACK12 = 1; } //----------------------------------------------------------------------------------- // ISR to handle SYNC1 ISR //----------------------------------------------------------------------------------- interrupt void ESC_applicationSync1ISR() { #ifdef ETHERCAT_STACK Sync1_Isr(); #endif //XINT4, PIE 12.INT2 PieCtrlRegs.PIEACK.bit.ACK12 = 1; } //----------------------------------------------------------------------------------- // Function to enable debug of SYNC0 signal on ControlCard configurations //----------------------------------------------------------------------------------- void ESC_enableSync0DebugOnCCARD(void) { //for debug of SYNC0 line.- the below code connects GPIO2 to the SYNC0 //internally because on the HW board we cannot put a scope on SYNC0 on HighRose connector //Connect SYNC0 (GPIO86) is INPUT1 for EALLOW; InputXbarRegs.INPUT1SELECT = ESC_SYNC0_GPIO; //input1 is tied to GPIO113 OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX1 = 0x1; //INPUTXBAR1 to OUTPUTXBAR1 OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX1 = 0x1; GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0x01; //GPIO2 to OUTPUTXBAR1 GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0x01; EDIS; } //----------------------------------------------------------------------------------- // Function to configure SYNC0 signal on ControlCard configurations //----------------------------------------------------------------------------------- void ESC_configureSync0GPIO(void) { GPIO_SetupPinOptions(ESC_SYNC0_GPIO, GPIO_INPUT, GPIO_PULLUP| GPIO_ASYNC); GPIO_SetupPinMux(ESC_SYNC0_GPIO, GPIO_MUX_CPU1, 0); EALLOW; InputXbarRegs.INPUT14SELECT = ESC_SYNC0_GPIO; //input14 is tied to XINT5 PieVectTable.XINT5_INT = &ESC_applicationSync0ISR; XintRegs.XINT5CR.bit.POLARITY = 1; // Falling edge interrupt XintRegs.XINT5CR.bit.ENABLE = 1; PieCtrlRegs.PIEIER12.bit.INTx3 = 1; // Enable Group 12, INT3 (XINT5) IER |= 0x0800; EDIS; // This is needed to disable write to EALLOW protected registers ESC_enableSync0DebugOnCCARD(); } //----------------------------------------------------------------------------------- // Function to enable debug of SYNC0 signal on ControlCard configurations //----------------------------------------------------------------------------------- void ESC_enableSync1DebugOnCCARD(void) { //for debug of SYNC1 line.- the below code connects GPIO3 to the SYNC1 //internally because on the HW board we cannot put a scope on SYNC1 on HighRose connector //Connect SYNC1 is INPUT1 for EALLOW; InputXbarRegs.INPUT2SELECT = ESC_SYNC1_GPIO; //input2 is tied to SYNC1 OutputXbarRegs.OUTPUT2MUX0TO15CFG.bit.MUX3 = 0x1; //INPUTXBAR2 to OUTPUTXBAR2 OutputXbarRegs.OUTPUT2MUXENABLE.bit.MUX3 = 0x1; GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0x01; //GPIO3 to OUTPUTXBAR2 GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0x01; EDIS; } //----------------------------------------------------------------------------------- // Function to configure SYNC1 signal on ControlCard configurations //----------------------------------------------------------------------------------- void ESC_configureSync1GPIO(void) { GPIO_SetupPinOptions(ESC_SYNC1_GPIO, GPIO_INPUT, GPIO_PULLUP| GPIO_ASYNC); GPIO_SetupPinMux(ESC_SYNC1_GPIO, GPIO_MUX_CPU1, 0); EALLOW; InputXbarRegs.INPUT13SELECT = ESC_SYNC1_GPIO; //input13 is tied to XINT4 PieVectTable.XINT4_INT = &ESC_applicationSync1ISR; XintRegs.XINT4CR.bit.POLARITY = 1; // Falling edge interrupt XintRegs.XINT4CR.bit.ENABLE = 1; PieCtrlRegs.PIEIER12.bit.INTx2 = 1; // Enable Group 12, INT2 (XINT4) IER |= 0x0800; EDIS; // This is needed to disable write to EALLOW protected registers ESC_enableSync1DebugOnCCARD(); } /***********************************************************************************/ void ESC_resetET1100(void) { GPIO_SetupPinMux(ESC_RESET_ET1100_GPIO, GPIO_MUX_CPU1, 0); GPIO_WritePin(ESC_RESET_ET1100_GPIO, 0); //hold reset low DELAY_US(500*1000); GPIO_WritePin(ESC_RESET_ET1100_GPIO, 1); //release reset DELAY_US(500*1000); } /***********************************************************************************/ uint16_t ESC_ET1100EEPROMLoadedCheck(void) { uint16_t ii = 0; GPIO_SetupPinMux(ESC_EEPROM_LOADED_GPIO, GPIO_MUX_CPU1, 0); while(!GPIO_ReadPin(ESC_EEPROM_LOADED_GPIO)) { DELAY_US(500*1000); ii++; if(ii > 10) break; } if(ii > 10) return 0; else return 1; } /***********************************************************************************/ void ESC_passFailSignalSetup(void) { // Note:- This function is not called when EMIF1 is used because there // is conflict with GPIO31 and GPIO34 with EMIF1 signals and LEDs // so with LAUNCHXL2.0 , user will only know if there is an error // Both LEDs (GPIO31 and GPIO34 HIGH or LOW always means no error on // Launchpad XL 2.0) GPIO_SetupPinMux(34, GPIO_MUX_CPU1, 0); GPIO_SetupPinMux(31, GPIO_MUX_CPU1, 0); GPIO_SetupPinOptions(34, 1, GPIO_OPENDRAIN | GPIO_PULLUP); GPIO_SetupPinOptions(31, 1, GPIO_OPENDRAIN | GPIO_PULLUP); //GPIO34 and GPIO31 at HIGH - means NO ERROR //keep GPIO31 and GPIO34 LOW for PASS - by default GpioDataRegs.GPADAT.bit.GPIO31 = 1; GpioDataRegs.GPBDAT.bit.GPIO34 = 1; } /***********************************************************************************/ void ESC_signalFail(void) { //Toggle GPIO34 and GPIO31 for fail GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; GpioDataRegs.GPATOGGLE.bit.GPIO31 = 1; DELAY_US(10 * 1000); } /***********************************************************************************/ void ESC_signalPass(void) { //keep GPIO31 and GPIO34 LOW for PASS GpioDataRegs.GPADAT.bit.GPIO31 = 1; GpioDataRegs.GPBDAT.bit.GPIO34 = 1; DELAY_US(500 * 1000); } //----------------------------------------------------------------------------------- // ISR to handle EPWM1 ISR // prdTick - EPWM1 Interrupts once every 4 QCLK counts (one period) //----------------------------------------------------------------------------------- interrupt void epwm1_isr(void) { if (int1cnt == 2) //10khz control loop frequency { EALLOW; //Uncomment the following lines to enable reading the values of the 3rd encoder //----------------------------------------------------------------------------- // // 3rd Encoder Read // // Read raw values of eQEPs // qep_posspeed.calc(&qep_posspeed); // // //Read raw position eQEP3 // if ((unsigned long int) qep_posspeed.raw_pos3 > pos_init) // raw_pos3 = (unsigned long int) qep_posspeed.raw_pos3 - pos_init; // else // raw_pos3 = -(pos_init - (unsigned long int) qep_posspeed.raw_pos3); // gwnia3 = 360.0f * (raw_pos3 * 8.0f * 26.0f) // / (2000.0f * 343.0f * 48.0f); //2000 lines //----------------------------------------------------------------------------- // Control Motor 1 Knee (BLDC) // 1st Encoder Read // Read raw values of eQEPs qep_posspeed.calc(&qep_posspeed); //Read raw position eQEP1 if ((unsigned long int) qep_posspeed.raw_pos1 > pos_init) raw_pos1 = (unsigned long int) qep_posspeed.raw_pos1 - pos_init; else raw_pos1 = -(pos_init - (unsigned long int) qep_posspeed.raw_pos1); angle_count1=raw_pos1; //Translate raw value to degrees gwnia1 = 360.0f * (raw_pos1 * 8.0f * 26.0f)/(2000.0f * 343.0f * 48.0f); //Normalize value of gwnia1 ngwnia1 = (gwnia1 * 1.0f) / 360.0f; // Run PID controller uk1 = DCL_runPID_C4(&pid1, rk1, ngwnia1, lk1); // Set direction if (uk1 >= 0.0f) GPIO_WritePin(DIR1_GPIO, 0); else { GPIO_WritePin(DIR1_GPIO, 1); uk1 = -uk1; } // Update PWM duty cycle //EPwm1Regs.CMPA.bit.CMPA = (1.0f - uk1) * SP; EPwm1Regs.CMPA.bit.CMPA = (1.0f-0.01*LED_Frequency) * SP; int1cnt = 0; } int1cnt++; EDIS; // Clear INT flag for this timer EPwm1Regs.ETCLR.bit.INT = 1; // // Acknowledge this __interrupt to receive more __interrupts from group 3 // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; } //----------------------------------------------------------------------------------- // ISR to handle EPWM2 ISR // prdTick - EPWM2 Interrupts once every 4 QCLK counts (one period) //----------------------------------------------------------------------------------- interrupt void epwm2_isr(void) { if (int2cnt == 2) //10khz control loop frequency { EALLOW; // Control Motor 2 Hip (Brushed DC) // Read raw values of eQEPs qep_posspeed.calc(&qep_posspeed); if ((unsigned long int) qep_posspeed.raw_pos2 > pos_init) raw_pos2 = (unsigned long int) qep_posspeed.raw_pos2 - pos_init; else raw_pos2 = -(pos_init - (unsigned long int) qep_posspeed.raw_pos2); //Translate raw value to degrees gwnia2 = 360.0f * (raw_pos2 * 12.0f * 26.0f)/(2000.0f * 637.0f * 48.0f); //Normalize value of gwnia2 ngwnia2 = (gwnia2 * 1.0f) / 360.0f; // Run PID controller uk2 = DCL_runPID_C4(&pid2, rk2, ngwnia2, lk2); // Set direction if (uk2 >= 0.0f) GPIO_WritePin(DIR2_GPIO, 0); else { GPIO_WritePin(DIR2_GPIO, 1); uk2 = -uk2; } // Update PWM duty cycle EPwm2Regs.CMPA.bit.CMPA = (1.0f - uk2) * SP; // Reset interrupt counter int2cnt = 0; } int2cnt++; EDIS; // Clear INT flag for this timer EPwm2Regs.ETCLR.bit.INT = 1; // // Acknowledge this __interrupt to receive more __interrupts from group 3 // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; } //----------------------------------------------------------------------------------- // Function to handle ADC Signals //----------------------------------------------------------------------------------- void ReadAnalog(void) { // //convert, wait for completion, and store results //start conversions immediately via software, ADCA // AdcaRegs.ADCSOCFRC1.all = 0x0003; //SOC0 and SOC1 // //start conversions immediately via software, ADCB // AdcbRegs.ADCSOCFRC1.all = 0x0003; //SOC0 and SOC1 // //wait for ADCA to complete, then acknowledge flag // while (AdcaRegs.ADCINTFLG.bit.ADCINT1 == 0) ; AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // //wait for ADCB to complete, then acknowledge flag // while (AdcbRegs.ADCINTFLG.bit.ADCINT1 == 0) ; AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // //store results // AdcaResult0 = AdcaResultRegs.ADCRESULT0; AdcaResult1 = AdcaResultRegs.ADCRESULT1; AdcbResult0 = AdcbResultRegs.ADCRESULT0; AdcbResult1 = AdcbResultRegs.ADCRESULT1; } /***********************************************************************************/ void ESC_initHW(void) { #ifdef FLASH // Copy time critical code and Flash setup code to RAM // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart // symbols are created by the linker. Refer to the linker files. memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (uint32_t)&RamfuncsLoadSize); #endif InitSysCtrl(); // Only used if running from FLASH // Note that the variable FLASH is defined by the compiler #ifdef FLASH // Call Flash Initialization to setup flash waitstates // This function must reside in RAM InitFlash(); // Call the flash wrapper init function #endif //(FLASH) // // enable PWM1, PWM2 and PWM3 // CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; // // Clear all __interrupts and initialize PIE vector table: // Disable CPU __interrupts // DINT; // Initialize the PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the F2837xD_PieCtrl.c file. InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: EALLOW; IER = 0x0000; IFR = 0x0000; EDIS; // Initialize the PIE vector table with pointers to the shell Interrupt // GService Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this example. This is useful for debug purposes. // The shell ISR routines are found in F2837xD_DefaultIsr.c. // This function is found in F2837xD_PieVect.c. InitPieVectTable(); EALLOW; // Initialize GPIO: // This example function is found in the F2837xD_Gpio.c file and // illustrates how to set the GPIO to its default state. // InitGpio(); // Skipped for this example GPIO_SetupPinMux(DIR1_GPIO, GPIO_MUX_CPU1, 0); GPIO_SetupPinOptions(DIR1_GPIO, GPIO_OUTPUT, GPIO_PUSHPULL); GPIO_SetupPinMux(DIR2_GPIO, GPIO_MUX_CPU1, 0); GPIO_SetupPinOptions(DIR2_GPIO, GPIO_OUTPUT, GPIO_PUSHPULL); // // For this case only init GPIO for eQEP1,2,3 and ePWM1,2 // This function is found in F2837xD_EQep.c // InitEQep1Gpio(); InitEQep2Gpio(); InitEQep3Gpio(); InitEPwm1Gpio(); InitEPwm2Gpio(); InitCpuTimers(); //------------------------------------------------------------------------------ //TxCnt=0; SPI_XmitInProgress=0; #ifdef USE_SPIA SpixRegs = &SpiaRegs; ESC_initSPIAGpio(); #elif USE_SPIC SpixRegs = &SpicRegs; ESC_initSPICGpio(); #else SpixRegs = &SpibRegs; ESC_initSPIBGpio(); #endif ESC_initSPIFIFO(); // Interrupts that are used in this example are re-mapped to // ISR functions found within this file. EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.XINT1_INT = &ESC_applicationLayerISR; PieVectTable.EPWM1_INT = &epwm1_isr; PieVectTable.EPWM2_INT = &epwm2_isr; EDIS; // This is needed to disable write to EALLOW protected registers // Initialize eQEP peripherals qep_posspeed.init(&qep_posspeed); // // Configure the ADC and power it up // CpuSysRegs.PCLKCR13.bit.ADC_A = 1; ConfigureADC(); // // Setup the ADCs for software conversions // SetupADCSoftware(); // Initialize ePWM peripherals EALLOW; CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; EDIS; initEpwm(); EALLOW; CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; EDIS; // Configure External Interrupt from ET1100 EALLOW; InputXbarRegs.INPUT4SELECT = ESC_SPI_INT_GPIO ; GPIO_SetupPinOptions(ESC_SPI_INT_GPIO, GPIO_INPUT, GPIO_PULLUP | GPIO_ASYNC); XintRegs.XINT1CR.bit.POLARITY = 0x0; // Falling edge interrupt XintRegs.XINT1CR.bit.ENABLE = 1; //EDIS; // // Enable CPU INT3 which is connected to EPWM1-3 INT: // IER |= M_INT3; // // Enable TINT0 in the PIE: Group 3 __interrupt 1 // PieCtrlRegs.PIEIER3.bit.INTx1 = 1; PieCtrlRegs.PIEIER3.bit.INTx2 = 1; //PieCtrlRegs.PIEIER3.bit.INTx3 = 1; // Enable interrupts required for this example PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable Group 1, INT4 (XINT1) IER |= 0x01; // Enable CPU INT1 EINT; // Enable Global Interrupts ERTM; // Enable Global realtime __interrupt DBGM ESC_passFailSignalSetup(); EALLOW; //CpuTimer0Regs.TCR.bit.TIE = 1; CpuTimer0Regs.TCR.bit.TSS = 0; //start timer ESC_configureSync0GPIO(); ESC_configureSync1GPIO(); // ESC_configureLatch0GPIO() // ESC_configureLatch1GPIO(); if(!ESC_ET1100EEPROMLoadedCheck()) { //EEPROM load failed //signal fail while(1) { //fail ESC_signalFail(); DELAY_US(500 * 1000); } } rk1 = 0.0f; //setpoint to 0 degrees rk2 = 0.0f; //DELAY_US(2*1000000); //wait for 2 sec } /***********************************************************************************/ Do you have any clue why is it causing this problem only when executing by FLASH? Thank you in advance Stamatis

Part Number: MSP430F6726 Hi community member, Please let me confirm the following a question for LCD Controller with MSP430F6726 . In the data sheet (p.70 LCD_C Recommended Operating Conditions), LCD frame frequency range (fFrame) is specified as follows: The frequency of the LCD module (fLCD) is calculated from CONDITIONS. (Min)fLCD = 2 x 4 x 0 = 0 (Max)fLCD = 2 x 4 x 100 = 800 Therefore, I understand that the recommended range of fLCD is 0 to 800 Hz. So, I have a question about fLCD [Question] if it is set to a frequency outside the recommended range (>800Hz), What happens to the MCU ? 1) Does abnormal operation or malfunction occur? Is the abnormal operation or malfunction temporary? For example, if I temporarily set fLCD to a frequency out of the recommended range and then restore it or reset MCU, Is that a problem? 2) Is there a possibility of an abnormal voltage being generated on the LCD module? Is there a possibility that the power supply voltage of the MCU will be exceeded when an abnormal voltage is generated? 3) The higher the fLCD, the higher the risk of 1), 2) occurring? I would be most grateful if you show graphs, figures, data etc when raising LCD module frequency. Thank you for your cooperation. Best regards, Cruijff

Thanks, I'll look into that. Is it really that the only way to program the MSP432E4 with the tools in CCS/SimpleLink SDK without JTAG is to use tools for other CPUs? I didn't really find a way to program it via the UART either (BSL scripter recognizes it but doesn't allow to do anything, and UniFlash doesn't have UART either?)

Hello Disona Thanks for your reply :) It becomes more clear to me now. I checked again and the pin is apparently connected to ADC C-2, so I changed my code to: AdccRegs.ADCSOC1CTL.bit.CHSEL = SENSE_Vout; //SOC1 will convert pin ADC C2 AdccRegs.ADCSOC1CTL.bit.ACQPS = acqps; AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 0x05; //Deze staat nu getriggerd op dezelfde als de ingangsspanningsmeting, kan/mag dit? But in the debug window, I have the impression that it's still not working. All my other ADC results are constantly blinking yellow and updating their measured values but this one does not do anything and has a constant value of 18084. Is it possible that the trigsel needs to be adapted somehow? I am now triggering on EPWM1, SOCA, which works fine for adc A0...

Hmm... The code looks fine to me. FYI you can use ADCSOC0CTL for ADC-C. Each ADC has its own SOCCTL registers. Have you called "AdcSetMode()" function with ADCb arguments in the beginning of your code? For example, this is how my code looks (checked and tested): // Trigger Timer Init EPwm4Regs.TBPRD = (CPU_FREQ / 2)* 1000 / ADC_OPS_FREQ / 2 - 1; // (200 MHz / 2 (EPWM clock is 100 MHz, not 200 MHz)) / 64 kHz / 2(UpDown) EPwm4Regs.ETSEL.bit.SOCAEN = 1; // enable SOCA EPwm4Regs.ETSEL.bit.SOCASEL = 1; // SOC when timer = 0 EPwm4Regs.ETPS.bit.SOCAPRD = 1; // generate pulse on 1st event EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // ADC init EALLOW; AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); // Non-differential signal, 12 bit resolution AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt right after S/H AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power-up ADC AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); // Non-differential signal, 12 bit resolution AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt right after S/H AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power-up ADC AdccRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); // Non-differential signal, 12 bit resolution AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt right after S/H AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power-up ADC // Setup ADC channels AdcaRegs.ADCSOC1CTL.bit.ACQPS = 10; // Sample-and-Hold Window: 10 cycles AdcaRegs.ADCSOC1CTL.bit.CHSEL = 14; // Channel ADCIN14 --- Udc AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 0xB; // Trigger - EPwm4 AdcbRegs.ADCSOC0CTL.bit.ACQPS = 10; // Sample-and-Hold Window: 10 cycles AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; // Channel ADCINB2 --- Ib AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 0xB; // Trigger - EPwm4 AdccRegs.ADCSOC0CTL.bit.ACQPS = 10; // Sample-and-Hold Window: 10 cycles AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; // Channel ADCINC2 --- Ia AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 0xB; // Trigger - EPwm4

Hello James, thanks for the help! As you said, i want to do the conditions (for example the start condition) with the GPIOs. I only want to do this, to see what happens on the bus. After i´ve seen that, i will always use USCI I2C module. But for learning purposes and i would like to see a code which does exactly this. I know it would be alot of work, so i was wondering if there is such a code floating around :) Best Regards Patrick

The USCI I2C module handles the start conditions. I would recommend using a logic analyzer to view this, and you can use a debugger like the MSP-FET to step through the code. Actually, Chapter 17 in the User's Guide has some good explanation on how everything works plus some helpful timing diagrams. Regards, James MSP Customer Applications

Excellent input. Regards, James MSP Customer Applications

Part Number: MSP430G2533 Hey guys, I am very new in the topic of CAN communicaiton and I have a question for my project. I want to send and receive data from my MSP430G2553 via CAN, so I use the MCP2515 controller and the SN65HVD231D transceiver. To realize the communication I connected the MCP2515 via SPI. Now I am confused about the Pins I need to use. Of course I will need the Pins for the SPI communication, TXCAN + RXCAN and INT (to use interrupts). But what do I need TX0RTS, TX1RTS, TX2RTS, RX0BF, RX1BF for? In the datasheet I read that these pins can be used as buffers or normal GPIOs, but I don't want to buffer anything, I just want to send and receive the data directly. Do I need these pins? If yes, how many do I need (I have a problem, because I don't have enough pins for my project, but if I don't need to use them all, I could use one of them) It would be great, if you could provide a very simple send and receive program for me. :) I would really appreciate your help! Best regards, Simon

Part Number: TMS320F28377D I am attempting to synchronize EPWM1-3 for a three-phase 208V inverter application. I followed the example code provided in ControlSuite (VSI - 1phase HP DC/AC), a modified the EPWM setup scripts. However, when I think I setup the EPWM IAW Chapter 14 of spruhm8g.pdf, I see a 20 ns delay in EPWM 2 and 3 from EPWM 1 (scope plot shown below, and option 1 in code snippet). Is this considered synchronized? If not, did I not setup the EPWM registers correctly? Also, when I setup the register in an alternative form (option 2 in code snippet), similar to that provided in the f803xPWM.h file that accompanies the three-phase motor control kit, I can get the three PWM pulses to line up exactly, but it doesn't appear to be IAW with the f28337xD documentation. Both cases give the correct output duty cycle and frequency. Any insight is appreciated. void setup3PPWM(uint16_t inv_pwm_no, uint16_t pwm_period_ticks, uint16_t pwm_dbred_ticks, uint16_t pwm_dbfed_ticks) { EALLOW; // PWM clock on F2837x is divided by 2 // ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1 //////////////////////////////////////////// // Time Base SubModule Registers //////////////////////////////////////////// (*ePWM[inv_pwm_no]).TBCTL.bit.PRDLD = TB_SHADOW; (*ePWM[inv_pwm_no]).TBPRD = pwm_period_ticks >>1; // PWM frequency = 1 / period (*ePWM[inv_pwm_no]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no]).TBCTR = 0; (*ePWM[inv_pwm_no]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; (*ePWM[inv_pwm_no]).TBCTL.bit.HSPCLKDIV = TB_DIV1; (*ePWM[inv_pwm_no]).TBCTL.bit.CLKDIV = TB_DIV1; (*ePWM[inv_pwm_no+1]).TBCTL.bit.PRDLD = TB_SHADOW; (*ePWM[inv_pwm_no+1]).TBPRD = pwm_period_ticks >>1; // PWM frequency = 1 / period (*ePWM[inv_pwm_no+1]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no+1]).TBCTR = 0; (*ePWM[inv_pwm_no+1]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; (*ePWM[inv_pwm_no+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1; (*ePWM[inv_pwm_no+1]).TBCTL.bit.CLKDIV = TB_DIV1; (*ePWM[inv_pwm_no+2]).TBCTL.bit.PRDLD = TB_SHADOW; (*ePWM[inv_pwm_no+2]).TBPRD = pwm_period_ticks >>1; // PWM frequency = 1 / period (*ePWM[inv_pwm_no+2]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no+2]).TBCTR = 0; (*ePWM[inv_pwm_no+2]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; (*ePWM[inv_pwm_no+2]).TBCTL.bit.HSPCLKDIV = TB_DIV1; (*ePWM[inv_pwm_no+2]).TBCTL.bit.CLKDIV = TB_DIV1; //Option 1 - Similar to TI documentation for f28377D (*ePWM[inv_pwm_no]).TBCTL.bit.PHSEN = TB_DISABLE; (*ePWM[inv_pwm_no+1]).TBCTL.bit.PHSEN = TB_ENABLE; (*ePWM[inv_pwm_no+2]).TBCTL.bit.PHSEN = TB_ENABLE; // configure PWM 2 and 3 as slaves and let it pass the sync in pulse from PWM1 (*ePWM[inv_pwm_no]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream" - like example document, but gives phase delay on scope (*ePWM[inv_pwm_no+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // - like example document, but gives phase delay on scope (*ePWM[inv_pwm_no+2]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // - like example document, but gives phase delay on scope //Option 2 - similar to f2803xPWM.h with 3-phase motor control kit //(*ePWM[inv_pwm_no]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // all set equal - pass through - this is how motor controller did it //(*ePWM[inv_pwm_no+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // all set equal - pass through - this is how motor controller did it //(*ePWM[inv_pwm_no+2]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // all set equal - pass through - this is how motor controller did it //(*ePWM[inv_pwm_no]).TBCTL.bit.PHSEN = TB_DISABLE; //(*ePWM[inv_pwm_no+1]).TBCTL.bit.PHSEN = TB_DISABLE; //(*ePWM[inv_pwm_no+2]).TBCTL.bit.PHSEN = TB_DISABLE; (*ePWM[inv_pwm_no]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no+1]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no+2]).TBPHS.bit.TBPHS = 0; (*ePWM[inv_pwm_no]).TBCTL.bit.PHSDIR = TB_UP; (*ePWM[inv_pwm_no+1]).TBCTL.bit.PHSDIR = TB_UP; (*ePWM[inv_pwm_no+2]).TBCTL.bit.PHSDIR = TB_UP; //////////////////////////////////////////// // Counter Compare Submodule Registers //////////////////////////////////////////// (*ePWM[inv_pwm_no]).CMPA.bit.CMPA = 0; // set duty 0% initially (*ePWM[inv_pwm_no]).CMPCTL.bit.SHDWAMODE = CC_SHADOW; (*ePWM[inv_pwm_no]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; //TLB Sample twice? (*ePWM[inv_pwm_no+1]).CMPA.bit.CMPA = 0; // set duty 0% initially (*ePWM[inv_pwm_no+1]).CMPCTL.bit.SHDWAMODE = CC_SHADOW; (*ePWM[inv_pwm_no+1]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; (*ePWM[inv_pwm_no+2]).CMPA.bit.CMPA = 0; // set duty 0% initially (*ePWM[inv_pwm_no+2]).CMPCTL.bit.SHDWAMODE = CC_SHADOW; (*ePWM[inv_pwm_no+2]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; //////////////////////////////////////////// // Action Qualifier SubModule Registers //////////////////////////////////////////// (*ePWM[inv_pwm_no]).AQCTLA.bit.CAU = AQ_CLEAR; // CTR = CMPA@UP , turn B on (GND out) (*ePWM[inv_pwm_no]).AQCTLA.bit.CAD = AQ_SET; // CTR = CMPA@Down , turn B off (V out) (*ePWM[inv_pwm_no+1]).AQCTLA.bit.CAU = AQ_CLEAR; // CTR = CMPA@UP , turn B on (GND out) (*ePWM[inv_pwm_no+1]).AQCTLA.bit.CAD = AQ_SET; // CTR = CMPA@Down , turn B off (V out) (*ePWM[inv_pwm_no+2]).AQCTLA.bit.CAU = AQ_CLEAR; // CTR = CMPA@UP , turn B on (GND out) (*ePWM[inv_pwm_no+2]).AQCTLA.bit.CAD = AQ_SET; // CTR = CMPA@Down , turn B off (V out) // to start don't configure the PWM to do anything //(*ePWM[inv_pwm_no]).AQCTLA.all = 0; //(*ePWM[inv_pwm_no+1]).AQCTLA.all = 0; //(*ePWM[inv_pwm_no+2]).AQCTLA.all = 0; //////////////////////////////////////////// // Active high complementary PWMs - Set up the deadband //////////////////////////////////////////// (*ePWM[inv_pwm_no]).DBCTL.bit.IN_MODE = DBA_ALL; (*ePWM[inv_pwm_no]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; (*ePWM[inv_pwm_no]).DBCTL.bit.POLSEL = DB_ACTV_HIC; (*ePWM[inv_pwm_no]).DBRED = pwm_dbred_ticks; (*ePWM[inv_pwm_no]).DBFED = pwm_dbred_ticks; (*ePWM[inv_pwm_no+1]).DBCTL.bit.IN_MODE = DBA_ALL; (*ePWM[inv_pwm_no+1]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; (*ePWM[inv_pwm_no+1]).DBCTL.bit.POLSEL = DB_ACTV_HIC; (*ePWM[inv_pwm_no+1]).DBRED = pwm_dbred_ticks; (*ePWM[inv_pwm_no+1]).DBFED = pwm_dbred_ticks; (*ePWM[inv_pwm_no+2]).DBCTL.bit.IN_MODE = DBA_ALL; (*ePWM[inv_pwm_no+2]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; (*ePWM[inv_pwm_no+2]).DBCTL.bit.POLSEL = DB_ACTV_HIC; (*ePWM[inv_pwm_no+2]).DBRED = pwm_dbred_ticks; (*ePWM[inv_pwm_no+2]).DBFED = pwm_dbred_ticks; EDIS; }

Part Number: TMS320F28377S Tool/software: Code Composer Studio I am trying to use the code for PI-CLA from C-2000 ware.When i set LS5 to be program memory from the code and then when i run the code the code run's into a section called illegal ISR and stops there This is the code that i am using /* Example_F28069_PI.c * * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ * ALL RIGHTS RESERVED * */ // header files #include "DCL.h" #include "cla_adc_fir32_shared.h" #include "F28x_Project.h" #include "stdio.h" // function prototypes interrupt void control_Isr(void); // global variables long IdleLoopCount = 0; long IsrCount = 0; float Duty=0; // shared variables #pragma DATA_SECTION(rk, "CpuToCla1MsgRAM") #pragma DATA_SECTION(yk, "CpuToCla1MsgRAM") #pragma DATA_SECTION(uk, "Cla1ToCpuMsgRAM") #pragma DATA_SECTION(pi1, "Cla1DataRam1") float rk = 0.25f; float yk=0.05f; float uk=0.00f; DCL_PI pi1 = PI_DEFAULTS; const struct PIE_VECT_TABLE PieVectTableInit = { PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved PIE_RESERVED_ISR, // Reserved TIMER1_ISR, // CPU Timer 1 Interrupt TIMER2_ISR, // CPU Timer 2 Interrupt DATALOG_ISR, // Datalogging Interrupt RTOS_ISR, // RTOS Interrupt EMU_ISR, // Emulation Interrupt NMI_ISR, // Non-Maskable Interrupt ILLEGAL_ISR, // Illegal Operation Trap USER1_ISR, // User Defined Trap 1 USER2_ISR, // User Defined Trap 2 USER3_ISR, // User Defined Trap 3 USER4_ISR, // User Defined Trap 4 USER5_ISR, // User Defined Trap 5 USER6_ISR, // User Defined Trap 6 USER7_ISR, // User Defined Trap 7 USER8_ISR, // User Defined Trap 8 USER9_ISR, // User Defined Trap 9 USER10_ISR, // User Defined Trap 10 USER11_ISR, // User Defined Trap 11 USER12_ISR, // User Defined Trap 12 ADCA1_ISR, // 1.1 - ADCA Interrupt 1 ADCB1_ISR, // 1.2 - ADCB Interrupt 1 ADCC1_ISR, // 1.3 - ADCC Interrupt 1 XINT1_ISR, // 1.4 - XINT1 Interrupt XINT2_ISR, // 1.5 - XINT2 Interrupt ADCD1_ISR, // 1.6 - ADCD Interrupt 1 TIMER0_ISR, // 1.7 - Timer 0 Interrupt WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt EPWM1_ISR, // 3.1 - ePWM1 Interrupt EPWM2_ISR, // 3.2 - ePWM2 Interrupt EPWM3_ISR, // 3.3 - ePWM3 Interrupt EPWM4_ISR, // 3.4 - ePWM4 Interrupt EPWM5_ISR, // 3.5 - ePWM5 Interrupt EPWM6_ISR, // 3.6 - ePWM6 Interrupt EPWM7_ISR, // 3.7 - ePWM7 Interrupt EPWM8_ISR, // 3.8 - ePWM8 Interrupt ECAP1_ISR, // 4.1 - eCAP1 Interrupt ECAP2_ISR, // 4.2 - eCAP2 Interrupt ECAP3_ISR, // 4.3 - eCAP3 Interrupt ECAP4_ISR, // 4.4 - eCAP4 Interrupt ECAP5_ISR, // 4.5 - eCAP5 Interrupt ECAP6_ISR, // 4.6 - eCAP6 Interrupt PIE_RESERVED_ISR, // 4.7 - Reserved PIE_RESERVED_ISR, // 4.8 - Reserved EQEP1_ISR, // 5.1 - eQEP1 Interrupt EQEP2_ISR, // 5.2 - eQEP2 Interrupt EQEP3_ISR, // 5.3 - eQEP3 Interrupt PIE_RESERVED_ISR, // 5.4 - Reserved PIE_RESERVED_ISR, // 5.5 - Reserved PIE_RESERVED_ISR, // 5.6 - Reserved PIE_RESERVED_ISR, // 5.7 - Reserved PIE_RESERVED_ISR, // 5.8 - Reserved SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt PIE_RESERVED_ISR, // 7.7 - Reserved PIE_RESERVED_ISR, // 7.8 - Reserved I2CA_ISR, // 8.1 - I2CA Interrupt 1 I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 I2CB_ISR, // 8.3 - I2CB Interrupt 1 I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt SCID_RX_ISR, // 8.7 - SCID Receive Interrupt SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt CANA0_ISR, // 9.5 - CANA Interrupt 0 CANA1_ISR, // 9.6 - CANA Interrupt 1 CANB0_ISR, // 9.7 - CANB Interrupt 0 CANB1_ISR, // 9.8 - CANB Interrupt 1 ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt ADCA2_ISR, // 10.2 - ADCA Interrupt 2 ADCA3_ISR, // 10.3 - ADCA Interrupt 3 ADCA4_ISR, // 10.4 - ADCA Interrupt 4 ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt ADCB2_ISR, // 10.6 - ADCB Interrupt 2 ADCB3_ISR, // 10.7 - ADCB Interrupt 3 ADCB4_ISR, // 10.8 - ADCB Interrupt 4 CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 XINT3_ISR, // 12.1 - XINT3 Interrupt XINT4_ISR, // 12.2 - XINT4 Interrupt XINT5_ISR, // 12.3 - XINT5 Interrupt PIE_RESERVED_ISR, // 12.4 - Reserved PIE_RESERVED_ISR, // 12.5 - Reserved VCU_ISR, // 12.6 - VCU Interrupt FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt PIE_RESERVED_ISR, // 1.9 - Reserved PIE_RESERVED_ISR, // 1.10 - Reserved PIE_RESERVED_ISR, // 1.11 - Reserved PIE_RESERVED_ISR, // 1.12 - Reserved IPC0_ISR, // 1.13 - IPC Interrupt 0 IPC1_ISR, // 1.14 - IPC Interrupt 1 IPC2_ISR, // 1.15 - IPC Interrupt 2 IPC3_ISR, // 1.16 - IPC Interrupt 3 EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt PIE_RESERVED_ISR, // 2.13 - Reserved PIE_RESERVED_ISR, // 2.14 - Reserved PIE_RESERVED_ISR, // 2.15 - Reserved PIE_RESERVED_ISR, // 2.16 - Reserved EPWM9_ISR, // 3.9 - ePWM9 Interrupt EPWM10_ISR, // 3.10 - ePWM10 Interrupt EPWM11_ISR, // 3.11 - ePWM11 Interrupt EPWM12_ISR, // 3.12 - ePWM12 Interrupt PIE_RESERVED_ISR, // 3.13 - Reserved PIE_RESERVED_ISR, // 3.14 - Reserved PIE_RESERVED_ISR, // 3.15 - Reserved PIE_RESERVED_ISR, // 3.16 - Reserved PIE_RESERVED_ISR, // 4.9 - Reserved PIE_RESERVED_ISR, // 4.10 - Reserved PIE_RESERVED_ISR, // 4.11 - Reserved PIE_RESERVED_ISR, // 4.12 - Reserved PIE_RESERVED_ISR, // 4.13 - Reserved PIE_RESERVED_ISR, // 4.14 - Reserved PIE_RESERVED_ISR, // 4.15 - Reserved PIE_RESERVED_ISR, // 4.16 - Reserved SD1_ISR, // 5.9 - SD1 Interrupt SD2_ISR, // 5.10 - SD2 Interrupt PIE_RESERVED_ISR, // 5.11 - Reserved PIE_RESERVED_ISR, // 5.12 - Reserved PIE_RESERVED_ISR, // 5.13 - Reserved PIE_RESERVED_ISR, // 5.14 - Reserved PIE_RESERVED_ISR, // 5.15 - Reserved PIE_RESERVED_ISR, // 5.16 - Reserved SPIC_RX_ISR, // 6.9 - *** Receive Interrupt SPIC_TX_ISR, // 6.10 - *** Transmit Interrupt PIE_RESERVED_ISR, // 6.11 - Reserved PIE_RESERVED_ISR, // 6.12 - Reserved PIE_RESERVED_ISR, // 6.13 - Reserved PIE_RESERVED_ISR, // 6.14 - Reserved PIE_RESERVED_ISR, // 6.15 - Reserved PIE_RESERVED_ISR, // 6.16 - Reserved PIE_RESERVED_ISR, // 7.9 - Reserved PIE_RESERVED_ISR, // 7.10 - Reserved PIE_RESERVED_ISR, // 7.11 - Reserved PIE_RESERVED_ISR, // 7.12 - Reserved PIE_RESERVED_ISR, // 7.13 - Reserved PIE_RESERVED_ISR, // 7.14 - Reserved PIE_RESERVED_ISR, // 7.15 - Reserved PIE_RESERVED_ISR, // 7.16 - Reserved PIE_RESERVED_ISR, // 8.9 - Reserved PIE_RESERVED_ISR, // 8.10 - Reserved PIE_RESERVED_ISR, // 8.11 - Reserved PIE_RESERVED_ISR, // 8.12 - Reserved PIE_RESERVED_ISR, // 8.13 - Reserved PIE_RESERVED_ISR, // 8.14 - Reserved #ifdef CPU1 UPPA_ISR, // 8.15 - uPPA Interrupt PIE_RESERVED_ISR, // 8.16 - Reserved #elif defined(CPU2) PIE_RESERVED_ISR, // 8.15 - Reserved PIE_RESERVED_ISR, // 8.16 - Reserved #endif PIE_RESERVED_ISR, // 9.9 - Reserved PIE_RESERVED_ISR, // 9.10 - Reserved PIE_RESERVED_ISR, // 9.11 - Reserved PIE_RESERVED_ISR, // 9.12 - Reserved PIE_RESERVED_ISR, // 9.13 - Reserved PIE_RESERVED_ISR, // 9.14 - Reserved #ifdef CPU1 USBA_ISR, // 9.15 - USBA Interrupt #elif defined(CPU2) PIE_RESERVED_ISR, // 9.15 - Reserved #endif PIE_RESERVED_ISR, // 9.16 - Reserved ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt ADCC2_ISR, // 10.10 - ADCC Interrupt 2 ADCC3_ISR, // 10.11 - ADCC Interrupt 3 ADCC4_ISR, // 10.12 - ADCC Interrupt 4 ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt ADCD2_ISR, // 10.14 - ADCD Interrupt 2 ADCD3_ISR, // 10.15 - ADCD Interrupt 3 ADCD4_ISR, // 10.16 - ADCD Interrupt 4 PIE_RESERVED_ISR, // 11.9 - Reserved PIE_RESERVED_ISR, // 11.10 - Reserved PIE_RESERVED_ISR, // 11.11 - Reserved PIE_RESERVED_ISR, // 11.12 - Reserved PIE_RESERVED_ISR, // 11.13 - Reserved PIE_RESERVED_ISR, // 11.14 - Reserved PIE_RESERVED_ISR, // 11.15 - Reserved PIE_RESERVED_ISR, // 11.16 - Reserved EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt }; // // InitPieVectTable - This function initializes the PIE vector table to a // known state and must be executed after boot time. // void InitPieVectTable(void) { Uint16 i; Uint32 *Source = (void *) &PieVectTableInit; Uint32 *Dest = (void *) &PieVectTable; // // Do not write over first 3 32-bit locations (these locations are // initialized by Boot ROM with boot variables) // Source = Source + 3; Dest = Dest + 3; EALLOW; for(i = 0; i 1ms to allow ADC time to power up // for(i = 0; i C2000 Linker -> Advanced Options -> Command File // Preprocessing -> --define #ifdef CLA_C // Define a size for the CLA scratchpad area that will be used // by the CLA compiler for local symbols and temps // Also force references to the special symbols that mark the // scratchpad are. CLA_SCRATCHPAD_SIZE = 0x100; --undef_sym=__cla_scratchpad_end --undef_sym=__cla_scratchpad_start #endif //CLA_C _Cla1Prog_Start = _Cla1funcsRunStart; MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 RAMM0 : origin = 0x000122, length = 0x0002DE RAMD0 : origin = 0x00B000, length = 0x000800 RAMD1 : origin = 0x00B800, length = 0x000800 /*RAMLS4 : origin = 0x00A000, length = 0x000800*/ /*RAMLS5 : origin = 0x00A800, length = 0x000800*/ RAMLS4_LS5 : origin = 0x00A000, length = 0x001000 RESET : origin = 0x3FFFC0, length = 0x000002 PAGE 1 : BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMGS0 : origin = 0x00C000, length = 0x001000 RAMGS1 : origin = 0x00D000, length = 0x001000 RAMGS2 : origin = 0x00E000, length = 0x001000 RAMGS3 : origin = 0x00F000, length = 0x001000 RAMGS4 : origin = 0x010000, length = 0x001000 RAMGS5 : origin = 0x011000, length = 0x001000 RAMGS6 : origin = 0x012000, length = 0x001000 RAMGS7 : origin = 0x013000, length = 0x001000 RAMGS8 : origin = 0x014000, length = 0x001000 RAMGS9 : origin = 0x015000, length = 0x001000 RAMGS10 : origin = 0x016000, length = 0x001000 RAMGS11 : origin = 0x017000, length = 0x001000 RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */ RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */ RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */ RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */ CANA_MSG_RAM : origin = 0x049000, length = 0x000800 CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080 } SECTIONS { codestart : > BEGIN, PAGE = 0 .text : >> RAMD0|RAMD1|RAMLS4_LS5, PAGE = 0 .cinit : > RAMM0, PAGE = 0 .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 .stack : > RAMM1, PAGE = 1 .ebss : > RAMLS2, PAGE = 1 .econst : > RAMLS3, PAGE = 1 .esysmem : > RAMLS3, PAGE = 1 Filter_RegsFile : > RAMGS0, PAGE = 1 /* CLA specific sections */ Cla1Prog : > RAMLS4_LS5, LOAD_START(_Cla1funcsLoadStart), LOAD_END(_Cla1funcsLoadEnd), LOAD_SIZE(_Cla1funcsLoadSize), RUN_START(_Cla1funcsRunStart), PAGE = 0 CLADataLS0 : > RAMLS0, PAGE=1 Cla1DataRam1 : > RAMLS1, PAGE=1 Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 /* The following section definition are for SDFM examples */ Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 #ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000 .TI.ramfunc : {} > RAMM0, PAGE = 0 #else ramfuncs : > RAMM0 PAGE = 0 #endif #endif #ifdef CLA_C /* CLA C compiler sections */ // // Must be allocated to memory the CLA has write access to // CLAscratch : { *.obj(CLAscratch) . += CLA_SCRATCHPAD_SIZE; *.obj(CLAscratch_end) } > RAMLS1, PAGE = 1 .scratchpad : > RAMLS1, PAGE = 1 .bss_cla : > RAMLS1, PAGE = 1 .const_cla : > RAMLS1, PAGE = 1 #endif //CLA_C } /* //=========================================================================== // End of file. //=========================================================================== */