Rajamurugan, That linker file looks good. Are you passing the .out or the .txt image to the host programmer as your application? The host programmer and kernel expect the application to be in a certain ASCII format which must be generated using a post-build step. More information on this can be found in Serial Flash Programming of C2000 Microcontrollers (Rev. H) section 3. Best, Alex
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Forum Post: RE: TMS320F28379S: Issue with Serial Flash Programming using SCI Bootloader example from C2000ware
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Forum Post: RE: TMS320F280049: Flash API Operate Question
[quote userid="549268" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486861/tms320f280049-flash-api-operate-question/5711657#5711657"]After a Flash Erase, if I write 0xFFFF (Can the FMC recognize that the updated value is the same as the erased state and skip the write?), can I later modify it to 0x0000 ?[/quote] No, you cannot, it will trigger an Ecc error. [quote userid="549268" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486861/tms320f280049-flash-api-operate-question/5711657#5711657"]If an address has already been programmed with a non- 0xFFFF value (e.g., 0x1234 ), what happens if I continuously write the same value ( 0x1234 )? Will an error occur, or can the FMC recognize that the intended update is the same and skip the write?[/quote] The ECC is calculated for 64-bit aligned address and the corresponding 64-bit data. Any data not supplied (within a given 64-bit aligned memory) is treated as 0xFFFF. So this scenaria can also trigger ECC error if you are not writing same value to all the corresponding address. Regards, Rajeshwary
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Forum Post: RE: TMS320F280041C: Removal of Flash read protection for sectors 8 to sectors 15 in Bank0 and Bank1
Hi, There is no read protection for sectors. Can you please provide more details about the issue you are facing? Regards, Rajeshwary
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Forum Post: RE: TMDSCNCD2808: Need Dock
Hello, Do we have any updates??
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Forum Post: RE: TMS320F280025: MotorControl SDK - Identification of a ACIM
Question: Is it correct that the PWM is completely turned off during inductance and Rr calibration? Because that is what the estimator seems to do and then it nears some value that could make sense, but I don't see how it does that with disabling PWM?
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Forum Post: AM2632-Q1: AM2632-Q1 UART Wakeup for BQ79616
Part Number: AM2632-Q1 Other Parts Discussed in Thread: BQ79616 , Tool/software: Hello TI team, We are currently using AM2632-Q1 communicating with BQ79616 AFE. Based on the sample code provided for TMS570 + BQ79616, the procedure to wake up the BQ79616 from sleep mode is: Switch the MCU’s UART RX pin to GPIO mode. Drive the pin Low for a short period to trigger the AFE wake-up. Switch the pin back to UART mode for normal communication. Does TI provide any sample code or guidance on how to implement this UART-to-GPIO switching on AM2632-Q1? Are there recommended drivers or APIs in MCAL / SDK to handle this pin muxing dynamically? Any suggestions or examples would be greatly appreciated. Thank you!
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Forum Post: RE: MSP430FR58671: Baud Rate issue
> CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK; > UCA1CTLW0 |= UCSSEL__ACLK; // CLK = ACLK > UCA1BR1 = 0; This sets the UART BRCLK to be the VLO, which runs at ~10kHz, but with a variation of +/-50%. Divided by /1 (UCA1BR=0) you get something vaguely resembling 10kbps (not too far from 9.6kbps). The VLO frequency varies from device to device (as well as temperature/voltage), so I think you hit it lucky with the first device. Example msp430fr59xx_euscia0_uart_02.c configures the UART to 9600bps assuming a 32kHz crystal; I'm assuming you have one of those since you're enabling the LFXT: https://dev.ti.com/tirex/explore/node?node=A__AK5Xil4JGgeLwhF4rpGqvQ__msp430ware__IOGqZri__LATEST
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Forum Post: RE: TMS320F2800156-Q1: Differential sensor into single ended ADC inputs without differential/single ended amplifier circuit
Hi David, Are you running any example from C2000ware? Did you change ADC config to Differential input? Thanks, Susmitha
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Forum Post: RE: UNIFLASH: Memory Dump Guide for Different Packages
Hello, [quote userid="638035" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1488908/uniflash-memory-dump-guide-for-different-packages"]I was able to view the memory of the LP-MSPM0L1306 using Uniflash. This EVM comes in a 32-VQFN package. Is there a way to view the memory of the 24-VQFN package as well?[/quote] The package type typically does not matter. [quote userid="638035" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1488908/uniflash-memory-dump-guide-for-different-packages"]2. Can you recommend a socket for QFN24 that can connect to the EVM?[/quote] I will bring this thread to the attention of the MSP experts to comment further. Thanks ki
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Forum Post: RE: TMS320F280049C: TMS320F280049C-56RSH
Hi Nibesh, I am looking into this thread. I will reply back shortly. Thanks, Susmitha
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Forum Post: RE: TMS320F28375D: Dual Core Sysconfig Project Setup
Thank you, this is exactly what I was looking for! This works fine when I set CPU1 and CPU2 to use different projects. However, whenever I set CPU1 and CPU2 to use the same project (but two separate cpu-specific build configurations), I encounter the following issue: Whenever I attempt to build CPU1's build configuration, it works fine. When I attempt to build CPU2's build configuration, it automatically switches to CPU1's build configuration and builds that. Therefore, when I try to debug, it attempts to build CPU1&2 build configurations, but in reality only builds CPU1 build configuration, and thus the CPU2 binary does not exist. When I close the system project, then this behavior stops (I can build cpu1 and cpu2 build configurations separately). But then I am back at the same issue as before (where CPU2 build configuration has no context of the CPU1 autogenerated code). Should I expect to be able to use the same project with two separate build configurations for each CPU? Or am I required to use separate projects for each core? Thanks you!
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Forum Post: RE: CCSTUDIO3: Automation using CCS
[quote userid="646605" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1488272/ccstudio3-automation-using-ccs/5716924#5716924"]1. Does CCS interface helps in building and capturing logs ? Then it shall be helpful. Kindly share me if you have some more examples related to this.[/quote] CCS Scripting lacks the full logging capability of DSS. [quote userid="646605" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1488272/ccstudio3-automation-using-ccs/5716924#5716924"] It can be triggered from Linux terminal ?[/quote] CCS Scripting is supported in Linux [quote userid="646605" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1488272/ccstudio3-automation-using-ccs/5716924#5716924"]2. Also share me pointer to DSS command interface .[/quote] https://software-dl.ti.com/ccs/esd/documents/users_guide/sdto_dss_handbook.html [quote userid="646605" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1488272/ccstudio3-automation-using-ccs/5716924#5716924"]3. For DSS using Jython, we can trigger the scripts from Linux terminal [/quote] There is a Jython implementation for Linux. Thanks ki
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Forum Post: RE: LAUNCHXL-F2800157: Update application with SCI
Hello, Yes, you can use SCI boot to update firmware on your device. We have specific documentation and SCI flash kernel examples that walk through how to do this. Please refer to this application note, which explains the idea and the software example (it refers to different devices, but the flow/principles are the same): https://www.ti.com/lit/an/sprabv4h/sprabv4h.pdf Refer to the section that discusses using the hex utility to generate a .txt file from your project (in your case, the blinky LED project). You essentially just need to add a post-build step in your blinky LED project's "project properties" that generates a .txt file whenever you build the project. This generated .txt file is what you would load onto the device using the serial flash programming tool after the device has booted in SCI boot mode and is ready to load the blinky application code (blinky .txt). The post-build step should look something link this (see the app note for details): "${CG_TOOL_HEX}" "${BuildArtifactFileName}" -boot -sci8 -a -o "${BuildArtifactFileBaseName}.txt" Note that the F280015x flash kernel example can be found in C2000Ware at this directory as you have already found, I believe: {C2000Ware}\driverlib\f280015x\examples\flash\ Best Regards, Allison
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Forum Post: RE: MSP-FET: giving unable to connect error
Hi Gary Gao, Let me know if you need any extra information other than those screenshots (in MSP_FET_failure.docx).
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Forum Post: RE: MSPM0C1103: wake from SHUTDOWN
Hi Diego. Thanks for the clarification.
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Forum Post: MSP430FR6989: LFXIN: external oscillator resilience test
Part Number: MSP430FR6989 Tool/software: Team, Could you please help with the below? As part of some resilience testing for the MSPP430 clock source: The MSP430FR6989 switches to the internal 32kHz clock when there is a resistance of less than 300kOhm in parallel with the chip input-side load capacitor (C105) and no longer uses the externally provided clock. Unfortunately, the internal clock is relatively imprecise. Also the MCU draws a fairly high current of about 150uA in this state. We would like to understand this behavior better. -What criteria does the MSP use to decide whether to use the internal clock? -Is it a documented behavior? WHere can we find the related doc? Thanks in advance, Anthony
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Forum Post: RE: MSP430FR5994: Limited program and RAM memory compared with datasheet
First question, i have tried this: at line 137 removed : LEARAM : origin = 0x2C00, length = 0x1000 - LEASTACK_SIZE at line 222 removed: .leaRAM : {} > LEARAM /* LEA RAM */ Sadly there is still same issue, I have inserted the file, what is wrong? Second question, thanks it's good If I could reach that second RAM it would be great to finish that project Edited lnk_msp430fr5994.cmd: /****************************************************************************/ /* SPECIFY THE SYSTEM MEMORY MAP */ /****************************************************************************/ MEMORY { TINYRAM : origin = 0xA, length = 0x16 BSL : origin = 0x1000, length = 0x800 INFOD : origin = 0x1800, length = 0x80 INFOC : origin = 0x1880, length = 0x80 INFOB : origin = 0x1900, length = 0x80 INFOA : origin = 0x1980, length = 0x80 RAM : origin = 0x1C00, length = 0x1000 FRAM : origin = 0x4000, length = 0xBF80 FRAM2 : origin = 0x10000,length = 0x33FF8 /* Boundaries changed to fix CPU47 */ JTAGSIGNATURE : origin = 0xFF80, length = 0x0004, fill = 0xFFFF BSLSIGNATURE : origin = 0xFF84, length = 0x0004, fill = 0xFFFF IPESIGNATURE : origin = 0xFF88, length = 0x0008, fill = 0xFFFF INT00 : origin = 0xFF90, length = 0x0002 INT01 : origin = 0xFF92, length = 0x0002 INT02 : origin = 0xFF94, length = 0x0002 INT03 : origin = 0xFF96, length = 0x0002 INT04 : origin = 0xFF98, length = 0x0002 INT05 : origin = 0xFF9A, length = 0x0002 INT06 : origin = 0xFF9C, length = 0x0002 INT07 : origin = 0xFF9E, length = 0x0002 INT08 : origin = 0xFFA0, length = 0x0002 INT09 : origin = 0xFFA2, length = 0x0002 INT10 : origin = 0xFFA4, length = 0x0002 INT11 : origin = 0xFFA6, length = 0x0002 INT12 : origin = 0xFFA8, length = 0x0002 INT13 : origin = 0xFFAA, length = 0x0002 INT14 : origin = 0xFFAC, length = 0x0002 INT15 : origin = 0xFFAE, length = 0x0002 INT16 : origin = 0xFFB0, length = 0x0002 INT17 : origin = 0xFFB2, length = 0x0002 INT18 : origin = 0xFFB4, length = 0x0002 INT19 : origin = 0xFFB6, length = 0x0002 INT20 : origin = 0xFFB8, length = 0x0002 INT21 : origin = 0xFFBA, length = 0x0002 INT22 : origin = 0xFFBC, length = 0x0002 INT23 : origin = 0xFFBE, length = 0x0002 INT24 : origin = 0xFFC0, length = 0x0002 INT25 : origin = 0xFFC2, length = 0x0002 INT26 : origin = 0xFFC4, length = 0x0002 INT27 : origin = 0xFFC6, length = 0x0002 INT28 : origin = 0xFFC8, length = 0x0002 INT29 : origin = 0xFFCA, length = 0x0002 INT30 : origin = 0xFFCC, length = 0x0002 INT31 : origin = 0xFFCE, length = 0x0002 INT32 : origin = 0xFFD0, length = 0x0002 INT33 : origin = 0xFFD2, length = 0x0002 INT34 : origin = 0xFFD4, length = 0x0002 INT35 : origin = 0xFFD6, length = 0x0002 INT36 : origin = 0xFFD8, length = 0x0002 INT37 : origin = 0xFFDA, length = 0x0002 INT38 : origin = 0xFFDC, length = 0x0002 INT39 : origin = 0xFFDE, length = 0x0002 INT40 : origin = 0xFFE0, length = 0x0002 INT41 : origin = 0xFFE2, length = 0x0002 INT42 : origin = 0xFFE4, length = 0x0002 INT43 : origin = 0xFFE6, length = 0x0002 INT44 : origin = 0xFFE8, length = 0x0002 INT45 : origin = 0xFFEA, length = 0x0002 INT46 : origin = 0xFFEC, length = 0x0002 INT47 : origin = 0xFFEE, length = 0x0002 INT48 : origin = 0xFFF0, length = 0x0002 INT49 : origin = 0xFFF2, length = 0x0002 INT50 : origin = 0xFFF4, length = 0x0002 INT51 : origin = 0xFFF6, length = 0x0002 INT52 : origin = 0xFFF8, length = 0x0002 INT53 : origin = 0xFFFA, length = 0x0002 INT54 : origin = 0xFFFC, length = 0x0002 RESET : origin = 0xFFFE, length = 0x0002 } /****************************************************************************/ /* Specify the LEA memory map */ /****************************************************************************/ #define LEASTACK_SIZE 0x138 MEMORY { LEASTACK : origin = 0x3C00 - LEASTACK_SIZE, length = LEASTACK_SIZE } /****************************************************************************/ /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ /****************************************************************************/ SECTIONS { GROUP(RW_IPE) { GROUP(READ_WRITE_MEMORY) { .TI.persistent : {} /* For #pragma persistent */ .cio : {} /* C I/O Buffer */ .sysmem : {} /* Dynamic memory allocation area */ } PALIGN(0x0400), RUN_START(fram_rw_start) GROUP(IPENCAPSULATED_MEMORY) { .ipestruct : {} /* IPE Data structure */ .ipe : {} /* IPE */ .ipe_const : {} /* IPE Protected constants */ .ipe:_isr : {} /* IPE ISRs */ } PALIGN(0x0400), RUN_START(fram_ipe_start) RUN_END(fram_ipe_end) RUN_END(fram_rx_start) } > 0x4000 .cinit : {} > FRAM /* Initialization tables */ .binit : {} > FRAM /* Boot-time Initialization tables */ .pinit : {} > FRAM /* C++ Constructor tables */ .init_array : {} > FRAM /* C++ Constructor tables */ .mspabi.exidx : {} > FRAM /* C++ Constructor tables */ .mspabi.extab : {} > FRAM /* C++ Constructor tables */ .text:_isr : {} > FRAM /* Code ISRs */ #ifndef __LARGE_DATA_MODEL__ .const : {} > FRAM /* Constant data */ #else .const : {} >> FRAM | FRAM2 /* Constant data */ #endif #ifndef __LARGE_CODE_MODEL__ .text : {} > FRAM /* Code */ #else .text : {} >> FRAM2 | FRAM /* Code */ #endif #ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000 #ifndef __LARGE_CODE_MODEL__ .TI.ramfunc : {} load=FRAM, run=RAM, table(BINIT) #else .TI.ramfunc : {} load=FRAM | FRAM2, run=RAM, table(BINIT) #endif #endif #endif .jtagsignature : {} > JTAGSIGNATURE .bslsignature : {} > BSLSIGNATURE GROUP(SIGNATURE_SHAREDMEMORY) { .ipesignature : {} /* IPE Signature */ .jtagpassword : {} /* JTAG Password */ } > IPESIGNATURE .bss : {} > RAM /* Global & static vars */ .data : {} > RAM /* Global & static vars */ .TI.noinit : {} > RAM /* For #pragma noinit */ .stack : {} > RAM (HIGH) /* Software system stack */ .tinyram : {} > TINYRAM /* Tiny RAM */ /* MSP430 INFO memory segments */ .infoA : type = NOINIT{} > INFOA .infoB : type = NOINIT{} > INFOB .infoC : type = NOINIT{} > INFOC .infoD : type = NOINIT{} > INFOD .leaStack : {} > LEASTACK (HIGH) /* LEA STACK */ /* MSP430 interrupt vectors */ .int00 : {} > INT00 .int01 : {} > INT01 .int02 : {} > INT02 .int03 : {} > INT03 .int04 : {} > INT04 .int05 : {} > INT05 .int06 : {} > INT06 .int07 : {} > INT07 .int08 : {} > INT08 .int09 : {} > INT09 .int10 : {} > INT10 .int11 : {} > INT11 .int12 : {} > INT12 .int13 : {} > INT13 .int14 : {} > INT14 .int15 : {} > INT15 .int16 : {} > INT16 .int17 : {} > INT17 LEA : { * ( .int18 ) } > INT18 type = VECT_INIT PORT8 : { * ( .int19 ) } > INT19 type = VECT_INIT PORT7 : { * ( .int20 ) } > INT20 type = VECT_INIT EUSCI_B3 : { * ( .int21 ) } > INT21 type = VECT_INIT EUSCI_B2 : { * ( .int22 ) } > INT22 type = VECT_INIT EUSCI_B1 : { * ( .int23 ) } > INT23 type = VECT_INIT EUSCI_A3 : { * ( .int24 ) } > INT24 type = VECT_INIT EUSCI_A2 : { * ( .int25 ) } > INT25 type = VECT_INIT PORT6 : { * ( .int26 ) } > INT26 type = VECT_INIT PORT5 : { * ( .int27 ) } > INT27 type = VECT_INIT TIMER4_A1 : { * ( .int28 ) } > INT28 type = VECT_INIT TIMER4_A0 : { * ( .int29 ) } > INT29 type = VECT_INIT AES256 : { * ( .int30 ) } > INT30 type = VECT_INIT RTC_C : { * ( .int31 ) } > INT31 type = VECT_INIT PORT4 : { * ( .int32 ) } > INT32 type = VECT_INIT PORT3 : { * ( .int33 ) } > INT33 type = VECT_INIT TIMER3_A1 : { * ( .int34 ) } > INT34 type = VECT_INIT TIMER3_A0 : { * ( .int35 ) } > INT35 type = VECT_INIT PORT2 : { * ( .int36 ) } > INT36 type = VECT_INIT TIMER2_A1 : { * ( .int37 ) } > INT37 type = VECT_INIT TIMER2_A0 : { * ( .int38 ) } > INT38 type = VECT_INIT PORT1 : { * ( .int39 ) } > INT39 type = VECT_INIT TIMER1_A1 : { * ( .int40 ) } > INT40 type = VECT_INIT TIMER1_A0 : { * ( .int41 ) } > INT41 type = VECT_INIT DMA : { * ( .int42 ) } > INT42 type = VECT_INIT EUSCI_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT TIMER0_A1 : { * ( .int44 ) } > INT44 type = VECT_INIT TIMER0_A0 : { * ( .int45 ) } > INT45 type = VECT_INIT ADC12_B : { * ( .int46 ) } > INT46 type = VECT_INIT EUSCI_B0 : { * ( .int47 ) } > INT47 type = VECT_INIT EUSCI_A0 : { * ( .int48 ) } > INT48 type = VECT_INIT WDT : { * ( .int49 ) } > INT49 type = VECT_INIT TIMER0_B1 : { * ( .int50 ) } > INT50 type = VECT_INIT TIMER0_B0 : { * ( .int51 ) } > INT51 type = VECT_INIT COMP_E : { * ( .int52 ) } > INT52 type = VECT_INIT UNMI : { * ( .int53 ) } > INT53 type = VECT_INIT SYSNMI : { * ( .int54 ) } > INT54 type = VECT_INIT .reset : {} > RESET /* MSP430 reset vector */ } /****************************************************************************/ /* MPU/IPE SPECIFIC MEMORY SEGMENT DEFINITONS */ /****************************************************************************/ #ifdef _IPE_ENABLE #define IPE_MPUIPLOCK 0x0080 #define IPE_MPUIPENA 0x0040 #define IPE_MPUIPPUC 0x0020 // Evaluate settings for the control setting of IP Encapsulation #if defined(_IPE_ASSERTPUC1) #if defined(_IPE_LOCK ) && (_IPE_ASSERTPUC1 == 0x08)) fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPPUC |IPE_MPUIPLOCK); #elif defined(_IPE_LOCK ) fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPLOCK); #elif (_IPE_ASSERTPUC1 == 0x08) fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPPUC); #else fram_ipe_enable_value = (IPE_MPUIPENA); #endif #else #if defined(_IPE_LOCK ) fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPLOCK); #else fram_ipe_enable_value = (IPE_MPUIPENA); #endif #endif // Segment definitions #ifdef _IPE_MANUAL // For custom sizes selected in the GUI fram_ipe_border1 = (_IPE_SEGB1>>4); fram_ipe_border2 = (_IPE_SEGB2>>4); #else // Automated sizes generated by the Linker fram_ipe_border2 = fram_ipe_end >> 4; fram_ipe_border1 = fram_ipe_start >> 4; #endif fram_ipe_settings_struct_address = Ipe_settingsStruct >> 4; fram_ipe_checksum = ~((fram_ipe_enable_value & fram_ipe_border2 & fram_ipe_border1) | (fram_ipe_enable_value & ~fram_ipe_border2 & ~fram_ipe_border1) | (~fram_ipe_enable_value & fram_ipe_border2 & ~fram_ipe_border1) | (~fram_ipe_enable_value & ~fram_ipe_border2 & fram_ipe_border1)); #endif #ifdef _MPU_ENABLE #define MPUPW (0xA500) /* MPU Access Password */ #define MPUENA (0x0001) /* MPU Enable */ #define MPULOCK (0x0002) /* MPU Lock */ #define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */ __mpu_enable = 1; // Segment definitions #ifdef _MPU_MANUAL // For custom sizes selected in the GUI mpu_segment_border1 = _MPU_SEGB1 >> 4; mpu_segment_border2 = _MPU_SEGB2 >> 4; mpu_sam_value = (_MPU_SAM0 > 4; mpu_segment_border2 = fram_rx_start >> 4; mpu_sam_value = 0x1573; // Info R, Seg3 RX, Seg2 RWX, Seg1 RW #else mpu_segment_border1 = fram_rx_start >> 4; mpu_segment_border2 = fram_rx_start >> 4; mpu_sam_value = 0x1513; // Info R, Seg3 RX, Seg2 R, Seg1 RW #endif #endif #ifdef _MPU_LOCK #ifdef _MPU_ENABLE_NMI mpu_ctl0_value = MPUPW | MPUENA | MPULOCK | MPUSEGIE; #else mpu_ctl0_value = MPUPW | MPUENA | MPULOCK; #endif #else #ifdef _MPU_ENABLE_NMI mpu_ctl0_value = MPUPW | MPUENA | MPUSEGIE; #else mpu_ctl0_value = MPUPW | MPUENA; #endif #endif #endif /****************************************************************************/ /* INCLUDE PERIPHERALS MEMORY MAP */ /****************************************************************************/ -l msp430fr5994.cmd
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Forum Post: RE: MSP430FR5994: Limited program and RAM memory compared with datasheet
You deleted the LEARAM region but didn't change the length of the RAM. Change that to include the LEARAM.
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Forum Post: RE: MSP430FR5994: Limited program and RAM memory compared with datasheet
Ok, got it! Thanks a lot, it's working flawlessly MSP430: Flash/FRAM usage is 10810 bytes. RAM usage is 4310 bytes.
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Forum Post: RE: MCU-PLUS-SDK-AM243X: How do we recognize the potential failure described in Eratta i2310
Hi Tushar, Any update? Thanks, Merril
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