Hello, The ESM registers for the group status registers are at address offsets 0x18, 0x1C and 0x20. These are implemented as an array of three 32-bit registers defined as "uint32 SR1[3U];" in the header file sl_regs_esm.h So, SR1[2] is the ESMSR3 register for group3 error status flags as described in the TRM. Regards, Sunil
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