1. & 2. The FLL method auto adjusts the PLL for varying frequency, hence this module was added. Please see the following documentation inside SDK file:///C:/ti/ C2000Ware _DigitalPower_SDK_1_03_00_00/docs/html/dplib_html/group___s_p_l_l__1_p_h___s_o_g_i___f_l_l.html 3. see www.ti.com/.../tidud61b.pdf section 3.1.2.6.1 Input Cap Compensation for PF Improvement Under Light Load For more details, it is adopted from TIDM-1007 , see training.ti.com/digitally-controlled-high-efficiency-and-high-power-density-pfc-circuits-part-2-0 also for further reading ieeexplore.ieee.org/.../ 4. This is not of a lot of consequence for 60Hz , and I do not think the design uses it. it's taken from Hartmann, M., S.d. Round, H. Ertl, and J.w. Kolar. "Digital Current Controller for a 1 MHz, 10 KW Three-Phase VIENNA Rectifier." IEEE Transactions on Power Electronics 24, no. 11 (2009): 2496-508. doi:10.1109/tpel.2009.2031437 which the customer can use for further reading.
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