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Forum Post: RE: CCS/MSP430I2041: SPI peripheral inconsistency

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// Configure GPIOs P1DIR |= BIT4; // Slave select pin P1SEL0 |= BIT5 | BIT6 | BIT7; // eUSCI_B0 Pin Function P1SEL1 &= ~(BIT5 | BIT6 | BIT7); // Configure eUSCI_B0 for SPI operation UCB0CTLW0 = UCSWRST; // **Put state machine in reset** UCB0CTLW0 |= UCMSB | UCMST | UCSYNC | UCCKPH; // Set MSB first, Set to master mode, Set to synchronous mode, set phase = 1 (mode 3) UCB0CTLW0 |= UCSSEL_2; // Set clock to SMCLK UCB0BR0 = 0x02; // clock divided by 2 UCB0BR1 = 0; // UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**

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