[quote user="Jens-Michael Gross"]My personal opinion is that the oteh rIV registers should behave the same way. There is no sense in writing to the IV register except if you intentionally want to clear ALL pending interrupts. If you loop unitl it returns 0, you need to do a read anyway. So the write makes no sense if it is indeed implemented to only clear one. However, I never tried myself on th4 timer IV or port pin IV registers.Perhaps it is a msitake in the users guide and propagated by copy/paste. Or wasted silicon.[/quote]At least on MSP430G2452, the manual seems to be wrong at this point. I made a test with CCR1 compare, CCR2 compare and TAR overflow interrupts requested simultaneously. Reading TAIV four times in a row gives 2, 4, 10, 0. Inserting a write (I tried writing 0 and -1) after the first read makes the subsequent reads to return 0. The manual is not consistent, TAIV is described as read-only elsewhere. And the IAR header files define TAIV as read-only, so my assembler reported an error on "MOV.W #0, &TAIV".
Maybe the port interrupt vectors in 5xxx MSPs behave in the same way, 2xxx MSPs do not have PxIV -- a pity, it is difficult to use more than one pin per port for interrupts, although one can quite reliably work around the problem of interrupts being lost due to read-modify-write PxIFG access. Rather off-topic here, but I have seen a related PORT3 erratum for some older chips which is not listed in silicon errata for other chips and I was curious whether it describes the read-modify-write problem and whether it has been fixed somehow in hardware -- I made a test and it showed that it has not been fixed.