Hi Ozio, Yes I use a piece of the C2000 WARE but it’s my own project (not based on the examples). For the linker: I use the CMD file from C2000 Ware (28004X_generic_ram.cmd) associated to another CMD file to switch some pieces of the code in Flash (Additional_commands_RAM.cmd) Here in attachment you’ll find the MAP file for more details. The goal of this configuration is: Debugged code loaded in FLASH Under debug function in RAM .CINIT in RAM due to possible changes during debug This is interesting when I’m able to download program only in RAM, download in FLASH when new debugged functions are switched in the Flash memory. By this mean, I can gain time because I avoid to erase and program the FLASH memory. When I work fully in FLASH, I found out also I’ve to set the option “Combine Sections during Program Load to increase performance”. Otherwise the .text is split in several parts and there is an error regarding the non-blank memory. Here some code used: in Additional_commands_RAM.cmd SECTIONS { SINTBL : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 dclfuncs : >> RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 DataLogSection : >> RAMLS5 | RAMLS6 | RAMLS7, PAGE = 1 align(2) /* Allocate IQ math areas: */ IQmath : > RAMLS0, PAGE = 0 /* Math Code */ IQmathTables : > FLASH_BANK0_SEC0, PAGE = 0 FLASHlibrary : { *rts2800_fpu32.lib (.text) *SYS_ml.lib (.text) } >> FLASH_BANK0_SEC0 | FLASH_BANK0_SEC1 | FLASH_BANK0_SEC3, PAGE = 0 } and in the 28004X_generic_ram.cmd MEMORY { PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */ BEGIN : origin = 0x000000, length = 0x000002 RAMM0 : origin = 0x0000F5, length = 0x00030B RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RESET : origin = 0x3FFFC0, length = 0x000002 /* Flash sectors: you can use FLASH for program memory when the RAM is filled up*/ /* BANK 0 */ FLASH_BANK0_SEC0 : origin = 0x080000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */ /* BANK 1 */ FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000 /* on-chip Flash */ PAGE 1 : BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 RAMLS7 : origin = 0x00B800, length = 0x000800 RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 RAMGS3 : origin = 0x012000, length = 0x002000 } /*You can arrange the .text, .cinit, .const, .pinit, .switch and .econst to FLASH when RAM is filled up.*/ SECTIONS { codestart : > BEGIN, PAGE = 0 .TI.ramfunc : > RAMM0 PAGE = 0 .text : >>RAMM0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 .cinit : > RAMM0, PAGE = 0 .pinit : > RAMM0, PAGE = 0 .switch : > RAMM0, PAGE = 0 .cio : > RAMLS0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 .ebss : > RAMLS5, PAGE = 1 .econst : > RAMLS5, PAGE = 1 .esysmem : > RAMLS5, PAGE = 1 ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 } /* //=========================================================================== // End of file. //=========================================================================== */ Looking forward to your feedback. Best Regards, Nico
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