This is more or less, irrelevant, because for FRAM are used quick read / write functions, there is no flash memory. What is your master device max MCLK, and what about FRAM waiting states. For changing port output CPUvX2 need 3 CPU cycles, it is far away from 20 MHz max SBW clock. You can put your project in working condition (without using cap + resistor combo on target device). And at the end, when everything is working OK, you can use scope for fine adjustment (with NOP's) of SBW shiftings. You can also use mailbox for data exchange between master and free running target device by existing SBW connection. There is also open source slau320/replicator ported to FRAM master on github, but I don't have link here, search for it.
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