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Forum Post: RE: CCS/TMS320F28069: Software Synchronization ECAP peripherals malfunction

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Cody, Thank you for your quick answer. For your better understanding I attach the entire eCAP peripheral configuration. The ePWM module is not configured previously. I do not understand how to disable the last ePWM synco signal to avoid the synchornization with the eCAP module, because, according to our synchronization scheme the SYNCI signal comes from the ePWM1 module. And if I want to synchronise the ePWM2 module with the ePWM1 module, intrinsically this SYNCO signal will arrive to the eCAP1 module. In this project I control a three-phase inverter, each branch is controlled by the ePWM1, ePWM2 and ePWM3 respectively. So, the three ePWMs modules are synchronized. void InitECAP (void) { EALLOW; // ========= Enable ECAP1/ECAP2/ECAP3 clocks ========= // SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1 ENABLED SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2 ENABLED SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3 ENABLED // ========= Enable ECAP1/ECAP2/ECAP3 pins as peripheral ========= // // Configure Qualification before MUX Register (SPRUH18G 1.5.2 Configuration Overview: pages 119-120) --> Avoid Spurious Edges from ECAP GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 2; // Sampling window of six samples each one has the sampling period GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 2; // Sampling window of six samples each one has the sampling period GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 2; // Sampling window of six samples each one has the sampling period GpioCtrlRegs.GPACTRL.bit.QUALPRD3 = 18; // Sampling period (GPIO24 to GPIO31) 0xFF=255 -> 510/90MHz=5.67us, 18 -> 36/90MHz=0.4us GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as ECAP1 GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as ECAP2 GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as ECAP3 EDIS; // ========= CAP1 configuration ========= // ECap1Regs.TSCTR = 0; ECap1Regs.CTRPHS = 0; ECap1Regs.ECCTL1.bit.FREE_SOFT = 1; // The counter will counter freely (=1) ECap1Regs.ECCTL1.bit.PRESCALE = 0; // The prescaler logic is completely by-passed ECap1Regs.ECCTL1.bit.CAPLDEN = 1; // Enable loading of CAP1-4 registers on a capture event ECap1Regs.ECCTL1.bit.CTRRST4 = 0; // CAP4 event doesn't reset the counter ECap1Regs.ECCTL1.bit.CAP4POL = 0; // ECAP1_CAP4 is not used ECap1Regs.ECCTL1.bit.CTRRST3 = 0; // CAP3 event doesn't reset the counter ECap1Regs.ECCTL1.bit.CAP3POL = 0; // ECAP1_CAP3 is not used ECap1Regs.ECCTL1.bit.CTRRST2 = 0; // CAP2 event doesn't reset the counter ECap1Regs.ECCTL1.bit.CAP2POL = 1; // ECAP1_CAP2_POL = FALLING EDGE ECap1Regs.ECCTL1.bit.CTRRST1 = 0; // CAP1 event doesn't reset the counter ECap1Regs.ECCTL1.bit.CAP1POL = 0; // ECAP1_CAP1_POL = RISING EDGE ECap1Regs.ECCTL2.bit.APWMPOL = 0; // Only applicable in APWM mode ECap1Regs.ECCTL2.bit.CAP_APWM = 0; // CAP operation mode ECap1Regs.ECCTL2.bit.SYNCO_SEL = 0; // Sync-out = Sync-in (pass through) ECap1Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable TSCTR = CTRPHS after a SYNCI event ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // TSCTR free-running ECap1Regs.ECCTL2.bit.REARM = 1; // Arms the sequence ECap1Regs.ECCTL2.bit.STOP_WRAP = 1; // Wrap after Capture Event (2) in continuous mode ECap1Regs.ECCTL2.bit.CONT_ONESHT = 0; // Continuous mode ECap1Regs.ECEINT.bit.CEVT1 = 1; // Enable Capture Event 1 as an Interrupt Source ECap1Regs.ECEINT.bit.CEVT2 = 1; // Enable Capture Event 2 as an Interrupt Source // ========= CAP2 configuration ========= // ECap2Regs.TSCTR = 0; ECap2Regs.CTRPHS = 10000; ECap2Regs.ECCTL1.bit.FREE_SOFT = 1; // The counter will counter freely (=1) ECap2Regs.ECCTL1.bit.PRESCALE = 0; // The prescaler logic is completely by-passed ECap2Regs.ECCTL1.bit.CAPLDEN = 1; // Enable loading of CAP1-4 registers on a capture event ECap2Regs.ECCTL1.bit.CTRRST4 = 0; // CAP4 event doesn't reset the counter ECap2Regs.ECCTL1.bit.CAP4POL = 0; // ECAP2_CAP4 is not used ECap2Regs.ECCTL1.bit.CTRRST3 = 0; // CAP3 event doesn't reset the counter ECap2Regs.ECCTL1.bit.CAP3POL = 0; // ECAP2_CAP3 is not used ECap2Regs.ECCTL1.bit.CTRRST2 = 0; // CAP2 event doesn't reset the counter ECap2Regs.ECCTL1.bit.CAP2POL = 1; // ECAP2_CAP2_POL = FALLING EDGE ECap2Regs.ECCTL1.bit.CTRRST1 = 0; // CAP1 event doesn't reset the counter ECap2Regs.ECCTL1.bit.CAP1POL = 0; // ECAP2_CAP1_POL = RISING EDGE ECap2Regs.ECCTL2.bit.APWMPOL = 0; // Only applicable in APWM mode ECap2Regs.ECCTL2.bit.CAP_APWM = 0; // CAP operation mode ECap2Regs.ECCTL2.bit.SYNCO_SEL = 0; // Sync-out = Sync-in (pass through) ECap2Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable TSCTR = CTRPHS after a SYNCI event ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; // TSCTR free-running ECap2Regs.ECCTL2.bit.REARM = 1; // Arms the sequence ECap2Regs.ECCTL2.bit.STOP_WRAP = 1; // Wrap after Capture Event (2) in continuous mode ECap2Regs.ECCTL2.bit.CONT_ONESHT = 0; // Continuous mode ECap2Regs.ECEINT.bit.CEVT1 = 1; // Enable Capture Event 1 as an Interrupt Source ECap2Regs.ECEINT.bit.CEVT2 = 1; // Enable Capture Event 2 as an Interrupt Source // ========= CAP3 configuration ========= // ECap3Regs.TSCTR = 0; ECap3Regs.CTRPHS = 0; ECap3Regs.ECCTL1.bit.FREE_SOFT = 1; // The counter will counter freely (=1) ECap3Regs.ECCTL1.bit.PRESCALE = 0; // The prescaler logic is completely by-passed ECap3Regs.ECCTL1.bit.CAPLDEN = 1; // Enable loading of CAP1-4 registers on a capture event ECap3Regs.ECCTL1.bit.CTRRST4 = 0; // CAP4 event doesn't reset the counter ECap3Regs.ECCTL1.bit.CAP4POL = 0; // ECAP3_CAP4 is not used ECap3Regs.ECCTL1.bit.CTRRST3 = 0; // CAP3 event doesn't reset the counter ECap3Regs.ECCTL1.bit.CAP3POL = 0; // ECAP3_CAP3 is not used ECap3Regs.ECCTL1.bit.CTRRST2 = 0; // CAP2 event doesn't reset the counter ECap3Regs.ECCTL1.bit.CAP2POL = 1; // ECAP3_CAP2_POL = FALLING EDGE ECap3Regs.ECCTL1.bit.CTRRST1 = 0; // CAP1 event doesn't reset the counter ECap3Regs.ECCTL1.bit.CAP1POL = 0; // ECAP3_CAP1_POL = RISING EDGE ECap3Regs.ECCTL2.bit.APWMPOL = 0; // Only applicable in APWM mode ECap3Regs.ECCTL2.bit.CAP_APWM = 0; // CAP operation mode ECap3Regs.ECCTL2.bit.SYNCO_SEL = 2; // Sync-out disable ECap3Regs.ECCTL2.bit.SYNCI_EN = 1; // Enable TSCTR = CTRPHS after a SYNCI event ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; // TSCTR free-running ECap3Regs.ECCTL2.bit.REARM = 1; // Arms the sequence ECap3Regs.ECCTL2.bit.STOP_WRAP = 1; // Wrap after Capture Event (2) in continuous mode ECap3Regs.ECCTL2.bit.CONT_ONESHT = 0; // Continuous mode ECap3Regs.ECEINT.bit.CEVT1 = 1; // Enable Capture Event 1 as an Interrupt Source ECap3Regs.ECEINT.bit.CEVT2 = 1; // Enable Capture Event 2 as an Interrupt Source // ======== ECAP modules synchronization ======= // // the sync chain with syncin/syncout doesn't work as described by manual (the signal doesn't propagate from eCAP1 to eCAP2 & eCAP3) ECap1Regs.ECCTL2.bit.SWSYNC = 1; ECap1Regs.ECCTL2.bit.SYNCI_EN = 0; ECap2Regs.ECCTL2.bit.SYNCI_EN = 0; ECap3Regs.ECCTL2.bit.SYNCI_EN = 0; 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