Britta: Thanks for your reply! Yes, the P6.0-P.7 diagrams look a lot more sensible with P6SEL.x routed to an input to the OR gate rather than "fighting" with the output of the OR gate as is shown in the P7.4-P7.7 diagrams. I'll update our code as necessary to drive CBPD.x here necessary and document why we're not driving for the other P6.x and P7.x pins. I'll also mark this issue as "Resolved" and I'll look forward to an update Datasheet one of these days. Atlant
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