Lucas, I simulated this behavior now and have to correct me a little bit based on simulation it is only critical if the "reta" instruction is located at addresses 0x45BFC, 0x45BFE. In the end it means that only the last 2 words should not be filled with instruction code and the last 4 words. I also confirmed this on silicon! The reason why I had seen the point also before at addresses 0x45BF8 and 0x45BFA is that the I had a breakpoint on the reta which will lead to additional flash accesses. But in free run mode or without debugger connected the "reta" should only be not located on 0x45BFC, 0x45BFE. Can you please confirm this. The root cause as mentioned before the pipelined CPU architecture and it's prefetching mechanism. On the top on this you have to know that the "reta" is an emulated MOVA @SP+,PC which takes 5 clocks. Looking at the instruction cycles there can be other instructions which takes a clock more e.g. mova &EDE,PC. For this the instruction should not be located on address 0x45BFA So finally said if you keep the last 8 words free or do not use it for instruction code it should work fine. But it would be enough for the "reta" to keep the last 2 words free. Please let me know if you can confirm this. Afterwards we will file this in our internal systems and decide how this is handled e.g. External ERRATA or Linker Command File fixes.....
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