Thomas, 1. The 200mA surge is not a condition that occurs in functional mode, so you don't need to consider this for purposes of Vdd variation while operating. That surge figure is from Table 5-19 of the MSP432P401 datasheet (Inrush current at startup). Designing for this 200mA in normal operating mode would be massively overdesign. 2. TI does not provide specific numbers in the datasheet for a given frequency of ripple on DVCC. I would refer you to the MSP432P401 datasheet (Table 5-30, Precision ADC Dynamic Parameters), which shows the Power supply rejection ratio (PSRR_AC), which is measured at 1kHz. 3. On _AVCC_ ripple at 500kHz, I would offer the same answer as (2) above in referring you to the PSRR_xx values for the impact of supply voltage ripple on the analog system. In general, the MSP432P4 LaunchPad power systems (decoupling caps) can be considered a good starting point for evaluation use. For achieving lowest noise on the analog systems, additional decoupling and/or separation of DVCC/AVCC may be needed, but the specifics will depend on your particular board design. The PSRR figures in the datasheet suggest that for "reasonable" input voltage ripple (a few %), the impact on the ADC will be quite small. The impact can be made even smaller (20x!) if using differential mode conversions. Hope that helps. This is all the information we can offer presently. Regards, - Bob L.
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