Hi Todd, I aligned the memory to 4 byte addresses but it still didn't work. The source code I used is the following: #pragma DATA_ALIGN(Adc0_FIFO0_UDMA_A, 4) uint16_t Adc0_FIFO0_UDMA_A[VJDMATRANSFERSIZE_SS0]; #pragma DATA_ALIGN(Adc0_FIFO1_UDMA_A, 4) uint16_t Adc0_FIFO1_UDMA_A[VJDMATRANSFERSIZE_SS1]; #pragma DATA_ALIGN(Adc1_FIFO0_UDMA_A, 4) uint16_t Adc1_FIFO0_UDMA_A[VJDMATRANSFERSIZE_SS0]; #pragma DATA_ALIGN(Adc1_FIFO1_UDMA_A, 4) uint16_t Adc1_FIFO1_UDMA_A[VJDMATRANSFERSIZE_SS1]; #pragma DATA_ALIGN(Adc0_FIFO0_UDMA_B, 4) uint16_t Adc0_FIFO0_UDMA_B[VJDMATRANSFERSIZE_SS0]; #pragma DATA_ALIGN(Adc0_FIFO1_UDMA_B, 4) uint16_t Adc0_FIFO1_UDMA_B[VJDMATRANSFERSIZE_SS1]; #pragma DATA_ALIGN(Adc1_FIFO0_UDMA_B, 4) uint16_t Adc1_FIFO0_UDMA_B[VJDMATRANSFERSIZE_SS0]; #pragma DATA_ALIGN(Adc1_FIFO1_UDMA_B, 4) uint16_t Adc1_FIFO1_UDMA_B[VJDMATRANSFERSIZE_SS1]; However I needed to proceed with my work and changed my memory management more to a way how I imagen the final programm should run. I allocate a whole block of memory and split this block into 8 memory blocks. In that way the arrays are in a consecutivley order. And it turned out that this is the solution to the problem. Here is the corresponding source code: /* * Copyright (c) 2015, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * ======== empty_min.c ======== */ /* XDCtools Header files */ #include #include #include #include /* BIOS Header files */ #include #include #include /* TI-RTOS Header files */ // #include #include // #include // #include // #include // #include // #include // #include // #include /* Board Header file */ #include "Board.h" /* */ #include //Variable definitions for C99 standard #include //Boolean definitions for the C99 standard #include "inc/tm4c129encpdt.h" #include "inc/hw_memmap.h" //Macros defining the memory map of Tiva C. #include "inc/hw_types.h" //Defines common types and macros #include "driverlib/sysctl.h" //Includes API functions such as SysCtlClockSet and SysCtlClockGet #include "driverlib/interrupt.h" //Defines for interrupt and register assignments #include "driverlib/gpio.h" //Includes API functions such as GPIOPinTypeGPIOOutput and GPIOPinWrite #include "driverlib/udma.h" /* Timer Header File */ #include "driverlib/timer.h" /* ADC Header File */ #include "driverlib/adc.h" /* Defines */ #define VJSYSFRQ 120000000 //CPU Frequency #define VJADCSINGLECHANNELRATE 50000 //Sample Rate of a single microphone channel #define VJNUMOFCHANNELS_SS0 8 //Number of Microphone channels served by AdcXSequencer0 #define VJNUMOFCHANNELS_SS1 2 //Number of Microphone channels served by AdcXSequencer1 #define VJDMATRANSFERSIZE_SS0 1024 //Number of items till a dma channel related to Sequencer 0 will cause an interrupt (AdcXSequencer0 interrupt) //In order that the samples of the 2 channels sampled by Sequencer1 are sent at the same time as the 8 sampled by Sequencer 1 the corresponding dma channel needs only to transfer 1/4th of the items of Sequencer0 #define VJDMATRANSFERSIZE_SS1 (VJDMATRANSFERSIZE_SS0/VJNUMOFCHANNELS_SS0)*VJNUMOFCHANNELS_SS1 //Number of items till a dma channel related to Sequencer 0 will cause an interrupt (AdcXSequencer1 interrupt) #define VJNUMOFSAMPLEPERTRANSFER VJDMATRANSFERSIZE_SS0/VJNUMOFCHANNELS_SS0 //Number of samples of one microphone channel in a single dma transfer /* Addresses of the FIFOs of the AdcXSequencerY */ #define VJADC0SS0FIFOADDRESS 0x40038048 #define VJADC0SS1FIFOADDRESS 0x40038068 #define VJADC1SS0FIFOADDRESS 0x40039048 #define VJADC1SS1FIFOADDRESS 0x40039068 /* * Prototypes */ void VJ_initAnalogInputs(void); void VJ_initADC0WithOutDMA(void); void VJ_initADC1WithOutDMA(void); void VJ_initADC0WithDMA(void); void VJ_initADC1WithDMA(void); void VJ_initTimer2ForADC(uint32_t ui32SysClkFreq); void ISR_Timer2(void); void ISR_Adc1Sequencer1(void); void ISR_Adc1Sequencer0(void); void ISR_Adc0Sequencer1(void); void ISR_Adc0Sequencer0(void); void VJ_initDMATransForADC1SS1(void); void VJ_initDMATransForADC1SS0(void); void VJ_initDMATransForADC0SS1(void); void VJ_initDMATransForADC0SS0(void); void SWI_Adc0Sequencer0(void); void SWI_Adc0Sequencer1(void); void SWI_Adc1Sequencer0(void); void SWI_Adc1Sequencer1(void); void VJ_initMemoryForDma(void); /* Debug Variable */ uint32_t TIMER2=0, ADC0SEQUENCER0=0, ADC0SEQUENCER1=0, ADC1SEQUENCER0=0, ADC1SEQUENCER1=0, ui32Mode=0, ADC0Sequencer0SWI=0, ADC0Sequencer1SWI=0, ADC0Sequencer0SWI_A=0, ADC0Sequencer0SWI_B=0,ADC0Sequencer1SWI_A=0,ADC0Sequencer1SWI_B=0, ADC1Sequencer0SWI=0, ADC1Sequencer1SWI=0, ADC1Sequencer0SWI_A=0, ADC1Sequencer0SWI_B=0,ADC1Sequencer1SWI_A=0,ADC1Sequencer1SWI_B=0, DebugPrint=0 ,DmaErrors=0; /* DMA Memory */ /* * First allocate the overall required memory, so the memory will be in a single block * Sequencer0 writes VJDMATRANSFERSIZE_SS0 items to memory * Sequencer1 writes VJDMATRANSFERSIZE_SS0/4=VJDMATRANSFERSIZE_SS1 items to memory * for each adc there is 1 Sequencer0 and 1 Sequencer1, both with an A and B buffer * Therefore the required array length equals: ADC0Sequencer0_A_Buffer->VJDMATRANSFERSIZE_SS0 * +ADC0Sequencer0_B_Buffer->VJDMATRANSFERSIZE_SS0 * +ADC1Sequencer0_A_Buffer->VJDMATRANSFERSIZE_SS0 * +ADC1Sequencer0_B_Buffer->VJDMATRANSFERSIZE_SS0 * +ADC0Sequencer1_A_Buffer->VJDMATRANSFERSIZE_SS1 * +ADC0Sequencer1_B_Buffer->VJDMATRANSFERSIZE_SS1 * +ADC1Sequencer1_A_Buffer->VJDMATRANSFERSIZE_SS1 * +ADC1Sequencer1_B_Buffer->VJDMATRANSFERSIZE_SS1 * ----------------------------------------------- * =4*VJDMATRANSFERSIZE_SS0+4*VJDMATRANSFERSIZE_SS1 */ uint16_t *p_u16_A_Memory, *p_u16_B_Memory, *p_u16_Adc0_Ss0_Udma_A, *p_u16_Adc1_Ss0_Udma_A, *p_u16_Adc0_Ss1_Udma_A, *p_u16_Adc1_Ss1_Udma_A, *p_u16_Adc0_Ss0_Udma_B, *p_u16_Adc1_Ss0_Udma_B, *p_u16_Adc0_Ss1_Udma_B, *p_u16_Adc1_Ss1_Udma_B; #pragma DATA_ALIGN(p_u16_AB_Memory, 4) uint16_t p_u16_AB_Memory[4*VJDMATRANSFERSIZE_SS0+4*VJDMATRANSFERSIZE_SS1]; void VJ_initMemoryForDma(void) { /* * Split the whole memory block into 2: p_u16_A_Memory->A_Buffer of length 2*VJDMATRANSFERSIZE_SS0+2*VJDMATRANSFERSIZE_SS1 * p_u16_B_Memory->B_Buffer of length 2*VJDMATRANSFERSIZE_SS0+2*VJDMATRANSFERSIZE_SS1 */ p_u16_A_Memory=&(p_u16_AB_Memory[0]); p_u16_B_Memory=&p_u16_AB_Memory[2*VJDMATRANSFERSIZE_SS0+2*VJDMATRANSFERSIZE_SS1]; /* * Split the A_Buffer into 4 memories: p_u16_Adc0_Ss0_Udma_A->A_Buffer for Adc0Sequencer0 of length VJDMATRANSFERSIZE_SS0 * p_u16_Adc1_Ss0_Udma_A->A_Buffer for Adc1Sequencer0 of length VJDMATRANSFERSIZE_SS0 * p_u16_Adc0_Ss1_Udma_A->A_Buffer for Adc0Sequencer1 of length VJDMATRANSFERSIZE_SS1 * p_u16_Adc1_Ss1_Udma_A->A_Buffer for Adc1Sequencer1 of length VJDMATRANSFERSIZE_SS1 */ p_u16_Adc0_Ss0_Udma_A=&(p_u16_A_Memory[0]); p_u16_Adc1_Ss0_Udma_A=&(p_u16_A_Memory[VJDMATRANSFERSIZE_SS0]); p_u16_Adc0_Ss1_Udma_A=&(p_u16_A_Memory[2*VJDMATRANSFERSIZE_SS0]); p_u16_Adc1_Ss1_Udma_A=&(p_u16_A_Memory[2*VJDMATRANSFERSIZE_SS0+VJDMATRANSFERSIZE_SS1]); /* * Split the B_Buffer into 4 memories: p_u16_Adc0_Ss0_Udma_B->B_Buffer for Adc0Sequencer0 of length VJDMATRANSFERSIZE_SS0 * p_u16_Adc1_Ss0_Udma_B->B_Buffer for Adc1Sequencer0 of length VJDMATRANSFERSIZE_SS0 * p_u16_Adc0_Ss1_Udma_B->B_Buffer for Adc0Sequencer1 of length VJDMATRANSFERSIZE_SS1 * p_u16_Adc1_Ss1_Udma_B->B_Buffer for Adc1Sequencer1 of length VJDMATRANSFERSIZE_SS1 */ p_u16_Adc0_Ss0_Udma_B=&(p_u16_B_Memory[0]); p_u16_Adc1_Ss0_Udma_B=&(p_u16_B_Memory[VJDMATRANSFERSIZE_SS0]); p_u16_Adc0_Ss1_Udma_B=&(p_u16_B_Memory[2*VJDMATRANSFERSIZE_SS0]); p_u16_Adc1_Ss1_Udma_B=&(p_u16_B_Memory[2*VJDMATRANSFERSIZE_SS0+VJDMATRANSFERSIZE_SS1]); } /* VJ_initAnalogInputs: put all 20 required pins to analog pins * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 * Port E: Pin0->AIN0 , Pin1->AIN1 , Pin2->AIN2 , Pin3->AIN3 , Pin4->AIN8 , Pin5->AIN9 * Port D: Pin0->AIN15, Pin1->AIN14 , Pin2->AIN13 , Pin3->AIN12 , Pin4->AIN7 , Pin5->AIN6 , Pin6->AIN5 , Pin7->AIN4 * Port K: Pin0->AIN16, Pin1->AIN17 , Pin2->AIN18 , Pin3->AIN19 * Port B: Pin4->AIN12, Pin5->AIN13 */ void VJ_initAnalogInputs(void) { while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOE)) { } while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)) { } while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOK)) { } while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)) { } // set Port E Pin 0 to 5 as analog input for AIN0 to AIN3 and AIN8 and AIN9 GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_4|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_5); // set Port D Pin 7,6,5,4,3,2,1,0 as analog input for AIN4, AIN5 ,AIN6 ,AIN7 ,AIN12 ,AIN13 ,AIN14 , AIN15 GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0); // set Port K Pin 0,1,2,3 as analog input for AIN16, AIN17, AIN18, AIN19 GPIOPinTypeADC(GPIO_PORTK_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); // set Port B Pin Pin 4,5 as analog input for AIN12 , AIN13 GPIOPinTypeADC(GPIO_PORTB_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); } void VJ_initADC0WithOutDMA(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)) { } //Configures the 0ths sequencer of ADC0 as triggered by a Timer with highest priority //ADC_adress|Sequencer_number|Trigger_source|Priority needs to be between 0 to 3, 0 highest prio; 3 lowest prio ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0); ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_TIMER, 1); //program sequencer 0 of ADC0 to sample AIN0 to AIN7 ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0); ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1); ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2); ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH3); ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH4); ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5); ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH6); ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH7|ADC_CTL_IE|ADC_CTL_END); //program sequencer 1 of ADC0 to sample AIN8 to AIN9 ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH8); ADCSequenceStepConfigure(ADC0_BASE, 1, 1, ADC_CTL_CH9|ADC_CTL_IE|ADC_CTL_END); ADCSequenceEnable(ADC0_BASE, 0);//enable sequencer 0 of ADC0 ADCSequenceEnable(ADC0_BASE, 1);//enable sequencer 1 of ADC0 ADCIntEnable(ADC0_BASE, 0); ADCIntEnable(ADC0_BASE, 1); IntEnable(INT_ADC0SS0);//enable the interrupt for sequencer0 of ADC0 IntEnable(INT_ADC0SS1);//enable the interrupt for sequencer1 of ADC0 } void VJ_initADC1WithOutDMA(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1); while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC1)) { } ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_TIMER, 0); ADCSequenceConfigure(ADC1_BASE, 1, ADC_TRIGGER_TIMER, 1); //program sequencer 0 of ADC1 to sample AIN10 to AIN17 ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH10); ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH11); ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH12); ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH13); ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH14); ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH15); ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH16); ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH17|ADC_CTL_IE|ADC_CTL_END); //program sequencer 1 of ADC1 to sample AIN0 to AIN7 ADCSequenceStepConfigure(ADC1_BASE, 1, 0, ADC_CTL_CH18); ADCSequenceStepConfigure(ADC1_BASE, 1, 1, ADC_CTL_CH19|ADC_CTL_IE|ADC_CTL_END); ADCSequenceEnable(ADC1_BASE, 0);//enable sequencer 0 of ADC1 ADCSequenceEnable(ADC1_BASE, 1);//enable sequencer 0 of ADC1 ADCIntEnable(ADC1_BASE, 0); ADCIntEnable(ADC1_BASE, 1); IntEnable(INT_ADC1SS0);//enable the interrupt for sequencer0 of ADC1 IntEnable(INT_ADC1SS1);//enable the interrupt for sequencer1 of ADC0 } void VJ_initADC0WithDMA(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)) { } //Configures the 0ths sequencer of ADC0 as triggered by a Timer with highest priority //ADC_adress|Sequencer_number|Trigger_source|Priority needs to be between 0 to 3, 0 highest prio; 3 lowest prio ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0); ADCSequenceConfigure(ADC0_BASE, 1, ADC_TRIGGER_TIMER, 1); //program sequencer 0 of ADC0 to sample AIN0 to AIN7 ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0); ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1); ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2); ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH3); ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH4); ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5); ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH6); ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH7|ADC_CTL_IE|ADC_CTL_END); //program sequencer 1 of ADC0 to sample AIN8 to AIN9 ADCSequenceStepConfigure(ADC0_BASE, 1, 0, ADC_CTL_CH8); ADCSequenceStepConfigure(ADC0_BASE, 1, 1, ADC_CTL_CH9|ADC_CTL_IE|ADC_CTL_END); //enable the adc to generate dma transfer requests //enable ADC0sequencer0 to request a dma transfer ADCSequenceDMAEnable(ADC0_BASE, 0); //enable ADC0sequencer1 to request a dma transfer ADCSequenceDMAEnable(ADC0_BASE, 1); ADCSequenceEnable(ADC0_BASE, 0);//enable sequencer 0 of ADC0 ADCSequenceEnable(ADC0_BASE, 1);//enable sequencer 1 of ADC0 ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS0);//enable the specific sequencer0 interrupt in ADC0 ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS1);//enable the specific sequencer1 interrupt in ADC0 } void VJ_initADC1WithDMA(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1); while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC1)) { } //Configures the 0ths sequencer of ADC1 as triggered by a Timer with highest priority //ADC_adress|Sequencer_number|Trigger_source|Priority needs to be between 0 to 3, 0 highest prio; 3 lowest prio ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_TIMER, 0); ADCSequenceConfigure(ADC1_BASE, 1, ADC_TRIGGER_TIMER, 1); //program sequencer 0 of ADC1 to sample AIN10 to AIN17 ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH10); ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH11); ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH12); ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH13); ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH14); ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH15); ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH16); ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH17|ADC_CTL_IE|ADC_CTL_END); //program sequencer 1 of ADC1 to sample AIN0 to AIN7 ADCSequenceStepConfigure(ADC1_BASE, 1, 0, ADC_CTL_CH18); ADCSequenceStepConfigure(ADC1_BASE, 1, 1, ADC_CTL_CH19|ADC_CTL_IE|ADC_CTL_END); //enable ADC1sequencer0 to request a dma transfer ADCSequenceDMAEnable(ADC1_BASE, 0); //enable ADC1sequencer1 to request a dma transfer ADCSequenceDMAEnable(ADC1_BASE, 1); ADCSequenceEnable(ADC1_BASE, 0);//enable sequencer 0 of ADC1 ADCSequenceEnable(ADC1_BASE, 1);//enable sequencer 0 of ADC1 ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS0);//enable the specific sequencer0 interrupt in ADC1 ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS1);//enable the specific sequencer1 interrupt in ADC1 } void VJ_initDMATransForADC1SS1(void) { uint8_t *CheckTable=0xFFFFFFFF; while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)) { } CheckTable=uDMAControlBaseGet(); if(CheckTable==0|CheckTable==0xFFFFFFFF) { while(1) {} } uDMAChannelAssign(UDMA_CH25_ADC1_1);//DMAChannel 25 is used by ADC1 Sequencer1 // disable all channel attributes for channel 14,15,24,25 uDMAChannelAttributeDisable(UDMA_SEC_CHANNEL_ADC11, UDMA_ATTR_ALL); /* enable for channel 14,15,24,25 burst mode->only burst modes will be processed by DMA *set the priority to high for channel 14 and 24, channel 15 and 25 will remain as default priority *the order of execution if multiple channels request a DMA are dependent on the channel number AND the priority setting, the lower the channel number the more important *Priority-List:0=most important,3=least important *-0. Channel 14 *-1. Channel 15 *-2. Channel 24 *-3. Channel 25 */ uDMAChannelAttributeEnable(UDMA_SEC_CHANNEL_ADC11, UDMA_ATTR_USEBURST); /* setup the primary control structure for channel 14,15,24,25 * a transfer item is 16 bit->UDMA_SIZE_16 * the sources are the FIFOs of the ADC sequencers, after a value is read from the FIFO this value is poped->UDMA_SRC_INC_NONE * the destination array is a uint16 array. each cell is 16 bit->UDMA_DST_INC_16 * the FIFOs request a DMA transfer if they are half full, for sequencer0 this is after 4 samples and for sequencer1 this is after 2 samples * the DMA should therefore always rearbitary after one burst if a higher priority channel requests a transfer-> UDMA_ARB_4 for sequencer 0, UDMA_ARB_2 for sequencer 1 */ uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC11|UDMA_PRI_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_2); /* setup the alternative control structure for channel 14,15,24,25 * the same settings as for the primary */ uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC11|UDMA_ALT_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_2); /* set second the primary transfer function active -> | UDMA_ALT_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the ping buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC11|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40039068, p_u16_Adc1_Ss1_Udma_B, VJDMATRANSFERSIZE_SS1); /* set second the primary transfer function active -> | UDMA_PRI_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the ping buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC11|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40039068, p_u16_Adc1_Ss1_Udma_A, VJDMATRANSFERSIZE_SS1); /* activate the channels * first transfer is with the primary control structure */ uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC11); } void VJ_initDMATransForADC1SS0(void) { uint8_t *CheckTable=0xFFFFFFFF; while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)) { } CheckTable=uDMAControlBaseGet(); if(CheckTable==0|CheckTable==0xFFFFFFFF) { while(1) {} } uDMAChannelAssign(UDMA_CH24_ADC1_0);//DMAChannel 24 is used by ADC1 Sequencer0 // disable all channel attributes for channel 14,15,24,25 uDMAChannelAttributeDisable(UDMA_SEC_CHANNEL_ADC10, UDMA_ATTR_ALL); /* enable for channel 14,15,24,25 burst mode->only burst modes will be processed by DMA *set the priority to high for channel 14 and 24, channel 15 and 25 will remain as default priority *the order of execution if multiple channels request a DMA are dependent on the channel number AND the priority setting, the lower the channel number the more important *Priority-List:0=most important,3=least important *-0. Channel 14 *-1. Channel 15 *-2. Channel 24 *-3. Channel 25 */ uDMAChannelAttributeEnable(UDMA_SEC_CHANNEL_ADC10, UDMA_ATTR_USEBURST|UDMA_ATTR_HIGH_PRIORITY); /* setup the primary control structure for channel 14,15,24,25 * a transfer item is 16 bit->UDMA_SIZE_16 * the sources are the FIFOs of the ADC sequencers, after a value is read from the FIFO this value is poped->UDMA_SRC_INC_NONE * the destination array is a uint16 array. each cell is 16 bit->UDMA_DST_INC_16 * the FIFOs request a DMA transfer if they are half full, for sequencer0 this is after 4 samples and for sequencer1 this is after 2 samples * the DMA should therefore always rearbitary after one burst if a higher priority channel requests a transfer-> UDMA_ARB_4 for sequencer 0, UDMA_ARB_2 for sequencer 1 */ uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10|UDMA_PRI_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_4); /* setup the alternative control structure for channel 14,15,24,25 * the same settings as for the primary */ uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10|UDMA_ALT_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_4); /* set second the primary transfer function active -> | UDMA_PRI_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the ping buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40039048, p_u16_Adc1_Ss0_Udma_A, VJDMATRANSFERSIZE_SS0); /* set first the alternative transfer function active -> | UDMA_ALT_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the pong buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40039048, p_u16_Adc1_Ss0_Udma_B, VJDMATRANSFERSIZE_SS0); /* activate the channels * first transfer is with the primary control structure */ uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC10); } void VJ_initDMATransForADC0SS1(void) { uint8_t *CheckTable=0xFFFFFFFF; while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)) { } CheckTable=uDMAControlBaseGet(); if(CheckTable==0|CheckTable==0xFFFFFFFF) { while(1) {} } uDMAChannelAssign(UDMA_CH15_ADC0_1);//DMAChannel 15 is used by ADC0 Sequencer1 // disable all channel attributes for channel 14,15,24,25 uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC1, UDMA_ATTR_ALL); /* enable for channel 14,15,24,25 burst mode->only burst modes will be processed by DMA *set the priority to high for channel 14 and 24, channel 15 and 25 will remain as default priority *the order of execution if multiple channels request a DMA are dependent on the channel number AND the priority setting, the lower the channel number the more important *Priority-List:0=most important,3=least important *-0. Channel 14 *-1. Channel 15 *-2. Channel 24 *-3. Channel 25 */ uDMAChannelAttributeEnable(UDMA_CHANNEL_ADC1, UDMA_ATTR_USEBURST); /* setup the primary control structure for channel 14,15,24,25 * a transfer item is 16 bit->UDMA_SIZE_16 * the sources are the FIFOs of the ADC sequencers, after a value is read from the FIFO this value is poped->UDMA_SRC_INC_NONE * the destination array is a uint16 array. each cell is 16 bit->UDMA_DST_INC_16 * the FIFOs request a DMA transfer if they are half full, for sequencer0 this is after 4 samples and for sequencer1 this is after 2 samples * the DMA should therefore always rearbitary after one burst if a higher priority channel requests a transfer-> UDMA_ARB_4 for sequencer 0, UDMA_ARB_2 for sequencer 1 */ uDMAChannelControlSet(UDMA_CHANNEL_ADC1|UDMA_PRI_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_2); /* setup the alternative control structure for channel 14,15,24,25 * the same settings as for the primary */ uDMAChannelControlSet(UDMA_CHANNEL_ADC1|UDMA_ALT_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_2); /* set second the primary transfer function active -> | UDMA_PRI_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the ping buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_CHANNEL_ADC1|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40038068, p_u16_Adc0_Ss1_Udma_A, VJDMATRANSFERSIZE_SS1); /* set first the alternative transfer function active -> | UDMA_ALT_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the pong buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_CHANNEL_ADC1|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40038068, p_u16_Adc0_Ss1_Udma_B, VJDMATRANSFERSIZE_SS1); /* activate the channels * first transfer is with the primary control structure */ uDMAChannelEnable(UDMA_CHANNEL_ADC1); } void VJ_initDMATransForADC0SS0(void) { uint8_t *CheckTable=0xFFFFFFFF; while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)) { } CheckTable=uDMAControlBaseGet(); if(CheckTable==0|CheckTable==0xFFFFFFFF) { while(1) {} } uDMAChannelAssign(UDMA_CH14_ADC0_0);//DMAChannel 14 is used by ADC0 Sequencer0 // disable all channel attributes for channel 14 uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC0, UDMA_ATTR_ALL);//TODO:DEBUG burst channel disabled /* enable for channel 14,15,24,25 burst mode->only burst modes will be processed by DMA *set the priority to high for channel 14 and 24, channel 15 and 25 will remain as default priority *the order of execution if multiple channels request a DMA are dependent on the channel number AND the priority setting, the lower the channel number the more important *Priority-List:0=most important,3=least important *-0. Channel 14 *-1. Channel 15 *-2. Channel 24 *-3. Channel 25 */ uDMAChannelAttributeEnable(UDMA_CHANNEL_ADC0, UDMA_ATTR_USEBURST|UDMA_ATTR_HIGH_PRIORITY); /* setup the primary control structure for channel 14,15,24,25 * a transfer item is 16 bit->UDMA_SIZE_16 * the sources are the FIFOs of the ADC sequencers, after a value is read from the FIFO this value is poped->UDMA_SRC_INC_NONE * the destination array is a uint16 array. each cell is 16 bit->UDMA_DST_INC_16 * the FIFOs request a DMA transfer if they are half full, for sequencer0 this is after 4 samples and for sequencer1 this is after 2 samples * the DMA should therefore always rearbitary after one burst if a higher priority channel requests a transfer-> UDMA_ARB_4 for sequencer 0, UDMA_ARB_2 for sequencer 1 */ uDMAChannelControlSet(UDMA_CHANNEL_ADC0|UDMA_PRI_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_4); /* setup the alternative control structure for channel 14,15,24,25 * the same settings as for the primary */ uDMAChannelControlSet(UDMA_CHANNEL_ADC0|UDMA_ALT_SELECT, UDMA_SIZE_16|UDMA_SRC_INC_NONE|UDMA_DST_INC_16|UDMA_ARB_4); /* set second the primary transfer function active -> | UDMA_PRI_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the ping buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_CHANNEL_ADC0|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40038048, p_u16_Adc0_Ss0_Udma_A, VJDMATRANSFERSIZE_SS0); /* set first the alternative transfer function active -> | UDMA_ALT_SELECT * Ping-Pong transfer -> UDMA_MODE_PINGPONG * source adresses -> FIFO adresse TODO:remove hard coded adresses * destination adresses -> adress of the first element of the pong buffers * number of items (16 bit) -> 1024 (WHICH IS THE MAXIMUM VALUE!) */ uDMAChannelTransferSet(UDMA_CHANNEL_ADC0|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40038048, p_u16_Adc0_Ss0_Udma_B, VJDMATRANSFERSIZE_SS0); /* activate the channels * first transfer is with the primary control structure */ uDMAChannelEnable(UDMA_CHANNEL_ADC0); } void VJ_initTimer2ForADC(uint32_t ui32SysClkFreq) { SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2); while(!SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER2)) { } uint32_t ui32Period = ui32SysClkFreq/VJADCSINGLECHANNELRATE; TimerConfigure(TIMER2_BASE, TIMER_CFG_PERIODIC);//configure timer2 as a periodic timer TimerLoadSet(TIMER2_BASE, TIMER_A, ui32Period-1);//load the calculated number of ticks into timer0 TimerControlTrigger(TIMER2_BASE, TIMER_A, true);//enables timer2 to trigger the ADCs TimerIntEnable(TIMER2_BASE, TIMER_TIMA_TIMEOUT);//enable the specific interrupt in timer0 TimerEnable(TIMER2_BASE, TIMER_A); } void ISR_Adc0Sequencer0(void) { ADCIntClear(ADC0_BASE,0);//TODO:Under- and Overflowcheck ADCIntClearEx(ADC0_BASE, ADC_INT_DMA_SS0); Swi_post(Adc0Sequencer0); ADC0SEQUENCER0++; } void ISR_Adc0Sequencer1(void) { ADCIntClear(ADC0_BASE,1);//TODO:Under- and Overflowcheck ADCIntClearEx(ADC0_BASE, ADC_INT_DMA_SS1); Swi_post(Adc0Sequencer1); ADC0SEQUENCER1++; } void ISR_Adc1Sequencer0(void) { ADCIntClear(ADC1_BASE,0);//TODO:Under- and Overflowcheck ADCIntClearEx(ADC1_BASE, ADC_INT_DMA_SS0); Swi_post(Adc1Sequencer0); ADC1SEQUENCER0++; } void ISR_Adc1Sequencer1(void) { ADCIntClear(ADC1_BASE,1);//TODO:Under- and Overflowcheck ADCIntClearEx(ADC1_BASE, ADC_INT_DMA_SS1); Swi_post(Adc1Sequencer1); ADC1SEQUENCER1++; } void ISR_Timer2(void) { // Clear the timer interrupt TimerIntClear(TIMER2_BASE, TIMER_TIMA_TIMEOUT); TIMER2++; DebugPrint=(TIMER2%(VJNUMOFSAMPLEPERTRANSFER)); switch (DebugPrint) { case 0: Log_info5("HWI !!! Timer2: [%u]| Adc0Sequencer0 : [%u] | Adc0Sequencer1 : [%u] | Adc1Sequencer0 : [%u] | Adc1Sequencer1 : [%u] ",TIMER2,ADC0SEQUENCER0,ADC0SEQUENCER1,ADC1SEQUENCER0,ADC1SEQUENCER1); break; case 1: Log_info5("SWI !!! Timer2: [%u]| Adc0Sequencer0_A: [%u] | Adc0Sequencer1_A: [%u] | Adc1Sequencer0_A: [%u] | Adc1Sequencer1_A: [%u] ",TIMER2,ADC0Sequencer0SWI_A,ADC0Sequencer1SWI_A,ADC1Sequencer0SWI_A,ADC1Sequencer1SWI_A); break; case 2: Log_info5("SWI !!! Timer2: [%u]| Adc0Sequencer0_B: [%u] | Adc0Sequencer1_B: [%u] | Adc1Sequencer0_B: [%u] | Adc1Sequencer1_B: [%u] ",TIMER2,ADC0Sequencer0SWI_B,ADC0Sequencer1SWI_B,ADC1Sequencer0SWI_B,ADC1Sequencer1SWI_B); break; case 3: Log_info5("DMA Enables!!! Timer2: [%u]| Adc0Sequencer0: [%u] | Adc0Sequencer1: [%u] | Adc1Sequencer0 : [%u] | Adc1Sequencer1 : [%u] ",TIMER2,ADC0Sequencer0SWI ,ADC0Sequencer1SWI ,ADC1Sequencer0SWI ,ADC1Sequencer1SWI ); break; } } void SWI_Adc0Sequencer0(void) { if(!uDMAChannelIsEnabled(UDMA_CHANNEL_ADC0)) { uDMAChannelEnable(UDMA_CHANNEL_ADC0); ADC0Sequencer0SWI++; } ui32Mode=uDMAChannelModeGet(UDMA_CHANNEL_ADC0|UDMA_PRI_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_CHANNEL_ADC0|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40038048, p_u16_Adc0_Ss0_Udma_A, VJDMATRANSFERSIZE_SS0); ADC0Sequencer0SWI_A++; } ui32Mode=uDMAChannelModeGet(UDMA_CHANNEL_ADC0|UDMA_ALT_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_CHANNEL_ADC0|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40038048, p_u16_Adc0_Ss0_Udma_B, VJDMATRANSFERSIZE_SS0); ADC0Sequencer0SWI_B++; } } void SWI_Adc0Sequencer1(void) { if(!uDMAChannelIsEnabled(UDMA_CHANNEL_ADC1)) { uDMAChannelEnable(UDMA_CHANNEL_ADC1); ADC0Sequencer1SWI++; } ui32Mode=uDMAChannelModeGet(UDMA_CHANNEL_ADC1|UDMA_PRI_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_CHANNEL_ADC1|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40038068, p_u16_Adc0_Ss1_Udma_A, VJDMATRANSFERSIZE_SS1); ADC0Sequencer1SWI_A++; } ui32Mode=uDMAChannelModeGet(UDMA_CHANNEL_ADC1|UDMA_ALT_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_CHANNEL_ADC1|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40038068, p_u16_Adc0_Ss1_Udma_B, VJDMATRANSFERSIZE_SS1); ADC0Sequencer1SWI_B++; } } void SWI_Adc1Sequencer0(void) { if(!uDMAChannelIsEnabled(UDMA_SEC_CHANNEL_ADC10)) { uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC10); ADC1Sequencer0SWI++; } ui32Mode=uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC10|UDMA_PRI_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40039048, p_u16_Adc1_Ss0_Udma_A, VJDMATRANSFERSIZE_SS0); ADC1Sequencer0SWI_A++; } ui32Mode=uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC10|UDMA_ALT_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40039048, p_u16_Adc1_Ss0_Udma_B, VJDMATRANSFERSIZE_SS0); ADC1Sequencer0SWI_B++; } } void SWI_Adc1Sequencer1(void) { if(!uDMAChannelIsEnabled(UDMA_SEC_CHANNEL_ADC11)) { uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC11); ADC1Sequencer1SWI++; } ui32Mode=uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC11|UDMA_PRI_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC11|UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, 0x40039068, p_u16_Adc1_Ss1_Udma_A, VJDMATRANSFERSIZE_SS1); ADC1Sequencer1SWI_A++; } ui32Mode=uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC11|UDMA_ALT_SELECT); if(ui32Mode==UDMA_MODE_STOP) { uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC11|UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, 0x40039068, p_u16_Adc1_Ss1_Udma_B, VJDMATRANSFERSIZE_SS1); ADC1Sequencer1SWI_B++; } } /* * ======== main ======== */ int main(void) { uint32_t ui32SysClkFreq = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), VJSYSFRQ); /* Call board init functions */ VJ_initMemoryForDma(); Board_initGeneral(); EK_TM4C129EXL_initDMA(); // Board_initEMAC(); Board_initGPIO(); // Board_initI2C(); // Board_initSDSPI(); // Board_initSPI(); // Board_initUART(); // Board_initUSB(Board_USBDEVICE); // Board_initUSBMSCHFatFs(); // Board_initWatchdog(); // Board_initWiFi(); VJ_initAnalogInputs(); VJ_initADC0WithDMA(); //VJ_initADC0WithOutDMA(); VJ_initDMATransForADC0SS0(); VJ_initDMATransForADC0SS1(); //VJ_initADC1WithOutDMA(); VJ_initADC1WithDMA(); VJ_initDMATransForADC1SS0(); VJ_initDMATransForADC1SS1(); VJ_initTimer2ForADC(ui32SysClkFreq); /* Start BIOS */ BIOS_start(); return (0); } So the problem itself is solved but I still don't understand why the memory needs to be structured in that way. Can you give me any insight in that, so I can avoid such problems in the future? Greetings Richard
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