Part Number: TMS570LC4357 Hi, i have a question regarding ESM error signalling timing. My customer has noticed that the ESM error / interrupt that is triggered by reading from the DED error region happens sometime after the offending load instruction is executed. Here is a sequence of instructions to illustrate the question: ld ..... // Read from OTP with intentional double ECC error dsb // Wait for all explicit memory accesses to complete nop // ESM2 bit not yet set / ESM high-level interrupt not fired nop // ESM2 bit not yet set / ESM high-level interrupt not fired nop // ESM2 bit not yet set / ESM high-level interrupt not fired nop // ESM2 bit not yet set / ESM high-level interrupt not fired nop // ESM2 bit not yet set / ESM high-level interrupt not fired nop // ESM2 bit set maybe / ESM high-level interrupt fired maybe nop // ... or maybe set / fired here nop // ... or maybe even here Any idea on why there is a delay in this getting triggered? Thanks TIDR
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