[quote user="Chee Chein Wong"]Base on my question, I am suspecting that the ADC digital block has to get the clock from the PLL in order for it to work properly.[/quote]Section 18.3.2.7 Module Clocking in the datasheet description of the ADC says: [quote]■ 16 MHz PIOSC. Using the PIOSC provides a conversion rate near 1 Msps. To use the PIOSC to clock the ADC, first power up the PLL and then enable the PIOSC in the CS bit field in the ADCCC register, then disable the PLL.[/quote]I.e. the PLL is necessary to initialise the ADC, but then should be able to be disabled.
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