Andy,
I did not forget about your question. I've done a lot of simulation to understand your problem.
Like I've explained in a previous post the problem is the way you disable the RTI Compare 0 interrupt.
Using the VIM Request Mask is the way to go.
Anyway, I will send you some waveform so you can see what is going on.
Apparently, there is a critical window of 1 HCLK cycle when the CPU acknowledge the RTI compare and the at the same time the RTI Interrupt enable is cleared.
Only under these circumstances the CPU will see another RTI interrupt.
Because of the pipeline structure, the speculative access and branch prediction, it is extremely difficult to evaluate from a software point of view when these condition are met.
I will try to prepare this report in the next few days and will be back to you.
