[quote user="mandar malve"]The STE pin is anyways will not be used for chip selection as it can be used as SPI Clock[/quote]
If STE isn’t used, then there is no difference between 3-wire and 4.-wire SPI. And if you use SPI for USCIA and USCIB, 4-wire mode is disabled/ignored anyway (as there are only 6 signal lines in total).
[quote user="mandar malve"]why should we use the chip select pin as any GPIO with interrupt is not understood.[/quote]If you are SPI slave, you surely want to know when the master is selecting you, so you can ASAP prepare the first data byte for the answer. You also might want to enable the MISO pin output, as you must not have this output active when not selected.
When the first clock edge arrives form the master, it is too late. That’s why an interrupt-capable port pin should be used.
If you are SPI master, you don’t need and can’t use 4-wire SPI at all and you don’t need interrupt capabilities on the CS pins. However, some slaves signal readiness by an independent interrupt line (e.g. ADC data ready) For this (which has nothing to do with SPI then) an interrupt-capable port pin might be a good idea too, unless you want to constantly poll the port for this signal (or want to ignore it)