[quote user="mh"]Is this expected behaviour? If so, why?[/quote]
This is indeed expected behavior.
If the ISR is called, the IFG bits are still set. So if GIE would stay set, the ISR would be immediately interrupted by the same interrupt. And again. There are only two interrupts where the IFG bit auto-clears: The Timer-A0 interrupt (as its only trigger is CCR0) and the ADC10 interrupt (here again only one Interrupt source). In all other cases, multiple triggers exist for the ISR and they need to be still set so you can determine which one was triggering the interrupt.