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Forum Post: RE: SVGEN and duty cycle

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The maximum modulation index is controlled by this define:

#define USER_MAX_VS_MAG_PU        (1.0)

and how this relates to maximum duty cycle and waveform shape is as follows:

USER_MAX_VS_MAG_PU = 1.0, Pure Sinewave Output, Maximum Duty Cycle = 86.6%

USER_MAX_VS_MAG_PU = 1.1547 (or 2/SQRT(3)), Pure Sinewave Output, Maximum Duty Cycle = 100.0%

USER_MAX_VS_MAG_PU = 1.3333 (or 4/3), Trapezoidal Output, Maximum Duty Cycle = 100.0%

As you can see, if you have this value set to > 1.1547. the output is not a sine wave anymore, so it will be no linear. If this is undesirable, stay with a maximum of 1.1547.

If your design cares about efficiency at high speeds, then you probably don't care about how linear it is, as long as it gives you more RMS voltage on the output, even if it's a trapezoidal voltage.

The challenge I think you are having is with current sensing, since a high duty cycle also means a very narrow pulse on the low side PWM, so the time you have to sample currents is reduced, actually it can even disappear.

A question to you, are you using two or three current sensors?

If you use three, you can run the ignore shunts function that we have in lab 10. That will allow you to sample currents even if the pulse gets narrow in our of the phases.

-Jorge


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